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add test to show suboptimal load merging behavior
[oota-llvm.git]
/
test
/
CodeGen
/
X86
/
zext-shl.ll
1
; RUN: llc < %s -march=x86 | FileCheck %s
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define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: shll
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; CHECK-NOT: movzwl
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; CHECK: ret
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%0 = zext i8 %x to i16
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%1 = shl i16 %0, 5
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%2 = zext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: shrl
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; CHECK-NOT: movzwl
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; CHECK: ret
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%0 = zext i8 %x to i16
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%1 = lshr i16 %0, 3
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%2 = zext i16 %1 to i32
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ret i32 %2
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}