1 ; RUN: llvm-as < %s | llc -march=x86-64 > %t
3 ; RUN: not grep movzbq %t
4 ; RUN: not grep movzwq %t
5 ; RUN: not grep movzlq %t
7 ; These should use movzbl instead of 'and 255'.
8 ; This related to not having a ZERO_EXTEND_REG opcode.
10 ; This test was split out of zext-inreg-0.ll because these
11 ; cases don't yet work on x86-32 due to the 8-bit subreg
14 define i32 @a(i32 %d) nounwind {
16 %retval = and i32 %e, 255
19 define i32 @b(float %d) nounwind {
20 %tmp12 = fptoui float %d to i8
21 %retval = zext i8 %tmp12 to i32
24 define i64 @d(i64 %d) nounwind {
26 %retval = and i64 %e, 255