1 ; RUN: llc < %s -march=x86 | not grep and
2 ; RUN: llc < %s -march=x86-64 > %t
4 ; RUN: not grep movzbq %t
5 ; RUN: not grep movzwq %t
6 ; RUN: not grep movzlq %t
8 ; These should use movzbl instead of 'and 255'.
9 ; This related to not having a ZERO_EXTEND_REG opcode.
11 define i32 @a(i32 %d) nounwind {
13 %retval = and i32 %e, 255
16 define i32 @b(float %d) nounwind {
17 %tmp12 = fptoui float %d to i8
18 %retval = zext i8 %tmp12 to i32
21 define i32 @c(i32 %d) nounwind {
23 %retval = and i32 %e, 65535
26 define i64 @d(i64 %d) nounwind {
28 %retval = and i64 %e, 255
31 define i64 @e(i64 %d) nounwind {
33 %retval = and i64 %e, 65535
36 define i64 @f(i64 %d) nounwind {
38 %retval = and i64 %e, 4294967295
42 define i32 @g(i8 %d) nounwind {
44 %retval = zext i8 %e to i32
47 define i32 @h(i16 %d) nounwind {
49 %retval = zext i16 %e to i32
52 define i64 @i(i8 %d) nounwind {
54 %retval = zext i8 %e to i64
57 define i64 @j(i16 %d) nounwind {
59 %retval = zext i16 %e to i64
62 define i64 @k(i32 %d) nounwind {
64 %retval = zext i32 %e to i64