1 ; RUN: llvm-as < %s | llc -march=x86 | not grep and
2 ; RUN: llvm-as < %s | llc -march=x86-64 > %t
4 ; RUN: not grep movzbq %t
5 ; RUN: not grep movzwq %t
6 ; RUN: not grep movzlq %t
8 ; These should use movzbl instead of 'and 255'.
9 ; This related to not having a ZERO_EXTEND_REG opcode.
11 define i32 @c(i32 %d) nounwind {
13 %retval = and i32 %e, 65535
16 define i64 @e(i64 %d) nounwind {
18 %retval = and i64 %e, 65535
21 define i64 @f(i64 %d) nounwind {
23 %retval = and i64 %e, 4294967295
27 define i32 @g(i8 %d) nounwind {
29 %retval = zext i8 %e to i32
32 define i32 @h(i16 %d) nounwind {
34 %retval = zext i16 %e to i32
37 define i64 @i(i8 %d) nounwind {
39 %retval = zext i8 %e to i64
42 define i64 @j(i16 %d) nounwind {
44 %retval = zext i16 %e to i64
47 define i64 @k(i32 %d) nounwind {
49 %retval = zext i32 %e to i64