1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
2 ; Verify that for the architectures that are known to have poor latency
3 ; double precision shift instructions we generate alternative sequence
4 ; of instructions with lower latencies instead of shrd instruction.
6 ;uint64_t rshift1(uint64_t a, uint64_t b)
8 ; return (a >> 1) | (b << 63);
13 ; CHECK-NEXT: shlq $63, {{.*}}
14 ; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
16 define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {
23 ;uint64_t rshift2(uint64_t a, uint64_t b)
25 ; return (a >> 2) | (b << 62);
29 ; CHECK: shrq $2, {{.*}}
30 ; CHECK-NEXT: shlq $62, {{.*}}
31 ; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
34 define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {
41 ;uint64_t rshift7(uint64_t a, uint64_t b)
43 ; return (a >> 7) | (b << 57);
47 ; CHECK: shrq $7, {{.*}}
48 ; CHECK-NEXT: shlq $57, {{.*}}
49 ; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
52 define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {
59 ;uint64_t rshift63(uint64_t a, uint64_t b)
61 ; return (a >> 63) | (b << 1);
64 ; CHECK-LABEL: rshift63:
65 ; CHECK: shrq $63, %rdi
66 ; CHECK-NEXT: leaq (%rdi,%rsi,2), %rax
68 define i64 @rshift63(i64 %a, i64 %b) nounwind readnone uwtable {