1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
2 ; Verify that for the architectures that are known to have poor latency
3 ; double precision shift instructions we generate alternative sequence
4 ; of instructions with lower latencies instead of shld instruction.
6 ;uint64_t lshift1(uint64_t a, uint64_t b)
8 ; return (a << 1) | (b >> 63);
11 ; CHECK-LABEL: lshift1:
12 ; CHECK: shrq $63, %rsi
13 ; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
15 define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable {
18 %shr = lshr i64 %b, 63
19 %or = or i64 %shr, %shl
23 ;uint64_t lshift2(uint64_t a, uint64_t b)
25 ; return (a << 2) | (b >> 62);
28 ; CHECK-LABEL: lshift2:
29 ; CHECK: shrq $62, %rsi
30 ; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax
32 define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable {
35 %shr = lshr i64 %b, 62
36 %or = or i64 %shr, %shl
40 ;uint64_t lshift7(uint64_t a, uint64_t b)
42 ; return (a << 7) | (b >> 57);
46 ; CHECK: shlq $7, {{.*}}
47 ; CHECK-NEXT: shrq $57, {{.*}}
48 ; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
50 define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable {
53 %shr = lshr i64 %b, 57
54 %or = or i64 %shr, %shl
58 ;uint64_t lshift63(uint64_t a, uint64_t b)
60 ; return (a << 63) | (b >> 1);
64 ; CHECK: shlq $63, {{.*}}
65 ; CHECK-NEXT: shrq {{.*}}
66 ; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
68 define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable {
72 %or = or i64 %shr, %shl