1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
4 target triple = "x86_64-unknown-unknown"
6 define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
7 ; SSE1-LABEL: shuffle_v4f32_0001:
9 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
11 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
12 ret <4 x float> %shuffle
14 define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
15 ; SSE1-LABEL: shuffle_v4f32_0020:
17 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
19 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
20 ret <4 x float> %shuffle
22 define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
23 ; SSE1-LABEL: shuffle_v4f32_0300:
25 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
27 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
28 ret <4 x float> %shuffle
30 define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
31 ; SSE1-LABEL: shuffle_v4f32_1000:
33 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
35 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
36 ret <4 x float> %shuffle
38 define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
39 ; SSE1-LABEL: shuffle_v4f32_2200:
41 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
43 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
44 ret <4 x float> %shuffle
46 define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
47 ; SSE1-LABEL: shuffle_v4f32_3330:
49 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
51 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
52 ret <4 x float> %shuffle
54 define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
55 ; SSE1-LABEL: shuffle_v4f32_3210:
57 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
59 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
60 ret <4 x float> %shuffle
62 define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) {
63 ; SSE1-LABEL: shuffle_v4f32_0011:
65 ; SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
67 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
68 ret <4 x float> %shuffle
70 define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) {
71 ; SSE1-LABEL: shuffle_v4f32_2233:
73 ; SSE1-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
75 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
76 ret <4 x float> %shuffle
78 define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
79 ; SSE1-LABEL: shuffle_v4f32_0022:
81 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,2]
83 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
84 ret <4 x float> %shuffle
86 define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
87 ; SSE1-LABEL: shuffle_v4f32_1133:
89 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3]
91 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
92 ret <4 x float> %shuffle
95 define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
96 ; SSE1-LABEL: shuffle_v4f32_4zzz:
98 ; SSE1-NEXT: xorps %xmm1, %xmm1
99 ; SSE1-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
100 ; SSE1-NEXT: movaps %xmm1, %xmm0
102 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
103 ret <4 x float> %shuffle
106 define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
107 ; SSE1-LABEL: shuffle_v4f32_z4zz:
109 ; SSE1-NEXT: xorps %xmm1, %xmm1
110 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
111 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
113 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
114 ret <4 x float> %shuffle
117 define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
118 ; SSE1-LABEL: shuffle_v4f32_zz4z:
120 ; SSE1-NEXT: xorps %xmm1, %xmm1
121 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
122 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
123 ; SSE1-NEXT: movaps %xmm1, %xmm0
125 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
126 ret <4 x float> %shuffle
129 define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
130 ; SSE1-LABEL: shuffle_v4f32_zuu4:
132 ; SSE1-NEXT: xorps %xmm1, %xmm1
133 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
134 ; SSE1-NEXT: movaps %xmm1, %xmm0
136 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
137 ret <4 x float> %shuffle
140 define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) {
141 ; SSE1-LABEL: shuffle_v4f32_zzz7:
143 ; SSE1-NEXT: xorps %xmm1, %xmm1
144 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
145 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
146 ; SSE1-NEXT: movaps %xmm1, %xmm0
148 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
149 ret <4 x float> %shuffle
152 define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
153 ; SSE1-LABEL: shuffle_v4f32_z6zz:
155 ; SSE1-NEXT: xorps %xmm1, %xmm1
156 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
157 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
159 %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
160 ret <4 x float> %shuffle
163 define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
164 ; SSE1-LABEL: insert_reg_and_zero_v4f32:
166 ; SSE1-NEXT: xorps %xmm1, %xmm1
167 ; SSE1-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
168 ; SSE1-NEXT: movaps %xmm1, %xmm0
170 %v = insertelement <4 x float> undef, float %a, i32 0
171 %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
172 ret <4 x float> %shuffle
175 define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
176 ; SSE1-LABEL: insert_mem_and_zero_v4f32:
178 ; SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
180 %a = load float, float* %ptr
181 %v = insertelement <4 x float> undef, float %a, i32 0
182 %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
183 ret <4 x float> %shuffle
186 define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
187 ; SSE1-LABEL: insert_mem_lo_v4f32:
189 ; SSE1-NEXT: movq (%rdi), %rax
190 ; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
191 ; SSE1-NEXT: shrq $32, %rax
192 ; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
193 ; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
194 ; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
195 ; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
196 ; SSE1-NEXT: xorps %xmm2, %xmm2
197 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
198 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
199 ; SSE1-NEXT: movaps %xmm1, %xmm0
201 %a = load <2 x float>, <2 x float>* %ptr
202 %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
203 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
204 ret <4 x float> %shuffle
207 define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
208 ; SSE1-LABEL: insert_mem_hi_v4f32:
210 ; SSE1-NEXT: movq (%rdi), %rax
211 ; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
212 ; SSE1-NEXT: shrq $32, %rax
213 ; SSE1-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
214 ; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
215 ; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
216 ; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
217 ; SSE1-NEXT: xorps %xmm2, %xmm2
218 ; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
219 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1]
221 %a = load <2 x float>, <2 x float>* %ptr
222 %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
223 %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
224 ret <4 x float> %shuffle
227 define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
228 ; SSE1-LABEL: shuffle_mem_v4f32_3210:
230 ; SSE1-NEXT: movaps (%rdi), %xmm0
231 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
233 %a = load <4 x float>, <4 x float>* %ptr
234 %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
235 ret <4 x float> %shuffle