1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: andps %xmm1, %xmm0
293 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: orps %xmm1, %xmm0
331 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: xorps %xmm1, %xmm1
356 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
357 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
360 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
362 ; SSSE3-NEXT: xorps %xmm1, %xmm0
363 ; SSSE3-NEXT: xorps %xmm1, %xmm1
364 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
365 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
368 ; SSE41-LABEL: combine_bitwise_ops_test3b:
370 ; SSE41-NEXT: xorps %xmm1, %xmm0
371 ; SSE41-NEXT: xorps %xmm1, %xmm1
372 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
375 ; AVX1-LABEL: combine_bitwise_ops_test3b:
377 ; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
378 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
379 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
382 ; AVX2-LABEL: combine_bitwise_ops_test3b:
384 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390 %xor = xor <4 x i32> %shuf1, %shuf2
394 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395 ; SSE2-LABEL: combine_bitwise_ops_test4b:
397 ; SSE2-NEXT: andps %xmm1, %xmm0
398 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
399 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
402 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
404 ; SSSE3-NEXT: andps %xmm1, %xmm0
405 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
406 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
409 ; SSE41-LABEL: combine_bitwise_ops_test4b:
411 ; SSE41-NEXT: andps %xmm1, %xmm0
412 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
413 ; SSE41-NEXT: movaps %xmm2, %xmm0
416 ; AVX1-LABEL: combine_bitwise_ops_test4b:
418 ; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
419 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
422 ; AVX2-LABEL: combine_bitwise_ops_test4b:
424 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
425 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
427 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
428 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429 %and = and <4 x i32> %shuf1, %shuf2
433 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
434 ; SSE2-LABEL: combine_bitwise_ops_test5b:
436 ; SSE2-NEXT: orps %xmm1, %xmm0
437 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
438 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
441 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
443 ; SSSE3-NEXT: orps %xmm1, %xmm0
444 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
445 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
448 ; SSE41-LABEL: combine_bitwise_ops_test5b:
450 ; SSE41-NEXT: orps %xmm1, %xmm0
451 ; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
452 ; SSE41-NEXT: movaps %xmm2, %xmm0
455 ; AVX1-LABEL: combine_bitwise_ops_test5b:
457 ; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
458 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
461 ; AVX2-LABEL: combine_bitwise_ops_test5b:
463 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
464 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
466 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
467 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
468 %or = or <4 x i32> %shuf1, %shuf2
472 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
473 ; SSE2-LABEL: combine_bitwise_ops_test6b:
475 ; SSE2-NEXT: xorps %xmm1, %xmm0
476 ; SSE2-NEXT: xorps %xmm1, %xmm1
477 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
478 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,1,3]
481 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
483 ; SSSE3-NEXT: xorps %xmm1, %xmm0
484 ; SSSE3-NEXT: xorps %xmm1, %xmm1
485 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
486 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,1,3]
489 ; SSE41-LABEL: combine_bitwise_ops_test6b:
491 ; SSE41-NEXT: xorps %xmm1, %xmm0
492 ; SSE41-NEXT: xorps %xmm1, %xmm1
493 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
494 ; SSE41-NEXT: movaps %xmm1, %xmm0
497 ; AVX1-LABEL: combine_bitwise_ops_test6b:
499 ; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
500 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
501 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
504 ; AVX2-LABEL: combine_bitwise_ops_test6b:
506 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
507 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
508 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
510 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
511 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
512 %xor = xor <4 x i32> %shuf1, %shuf2
516 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
517 ; SSE-LABEL: combine_bitwise_ops_test1c:
519 ; SSE-NEXT: andps %xmm1, %xmm0
520 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
523 ; AVX-LABEL: combine_bitwise_ops_test1c:
525 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
526 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
528 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
529 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
530 %and = and <4 x i32> %shuf1, %shuf2
534 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
535 ; SSE-LABEL: combine_bitwise_ops_test2c:
537 ; SSE-NEXT: orps %xmm1, %xmm0
538 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
541 ; AVX-LABEL: combine_bitwise_ops_test2c:
543 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
544 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
546 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
547 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
548 %or = or <4 x i32> %shuf1, %shuf2
552 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
553 ; SSE-LABEL: combine_bitwise_ops_test3c:
555 ; SSE-NEXT: xorps %xmm1, %xmm0
556 ; SSE-NEXT: xorps %xmm1, %xmm1
557 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
560 ; AVX-LABEL: combine_bitwise_ops_test3c:
562 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
563 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
564 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
566 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
567 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
568 %xor = xor <4 x i32> %shuf1, %shuf2
572 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
573 ; SSE-LABEL: combine_bitwise_ops_test4c:
575 ; SSE-NEXT: andps %xmm1, %xmm0
576 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
577 ; SSE-NEXT: movaps %xmm2, %xmm0
580 ; AVX-LABEL: combine_bitwise_ops_test4c:
582 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
583 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
585 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
586 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
587 %and = and <4 x i32> %shuf1, %shuf2
591 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
592 ; SSE-LABEL: combine_bitwise_ops_test5c:
594 ; SSE-NEXT: orps %xmm1, %xmm0
595 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
596 ; SSE-NEXT: movaps %xmm2, %xmm0
599 ; AVX-LABEL: combine_bitwise_ops_test5c:
601 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
602 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
604 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
605 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
606 %or = or <4 x i32> %shuf1, %shuf2
610 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
611 ; SSE-LABEL: combine_bitwise_ops_test6c:
613 ; SSE-NEXT: xorps %xmm1, %xmm0
614 ; SSE-NEXT: xorps %xmm1, %xmm1
615 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
616 ; SSE-NEXT: movaps %xmm1, %xmm0
619 ; AVX-LABEL: combine_bitwise_ops_test6c:
621 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
622 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
623 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
625 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
626 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
627 %xor = xor <4 x i32> %shuf1, %shuf2
631 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
632 ; SSE-LABEL: combine_nested_undef_test1:
634 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,1]
637 ; AVX-LABEL: combine_nested_undef_test1:
639 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,0,0,1]
641 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
642 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
646 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
647 ; SSE-LABEL: combine_nested_undef_test2:
649 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
652 ; AVX-LABEL: combine_nested_undef_test2:
654 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
656 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
657 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
661 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
662 ; SSE-LABEL: combine_nested_undef_test3:
664 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
667 ; AVX-LABEL: combine_nested_undef_test3:
669 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
671 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
672 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
676 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
677 ; SSE-LABEL: combine_nested_undef_test4:
679 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,1]
682 ; AVX-LABEL: combine_nested_undef_test4:
684 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,1]
686 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
687 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
691 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
692 ; SSE-LABEL: combine_nested_undef_test5:
694 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
697 ; AVX-LABEL: combine_nested_undef_test5:
699 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
701 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
702 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
706 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
707 ; SSE-LABEL: combine_nested_undef_test6:
709 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
712 ; AVX-LABEL: combine_nested_undef_test6:
714 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
716 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
717 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
721 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
722 ; SSE-LABEL: combine_nested_undef_test7:
724 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
727 ; AVX-LABEL: combine_nested_undef_test7:
729 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
731 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
732 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
736 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
737 ; SSE-LABEL: combine_nested_undef_test8:
739 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,3,0]
742 ; AVX-LABEL: combine_nested_undef_test8:
744 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,0]
746 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
747 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
751 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
752 ; SSE-LABEL: combine_nested_undef_test9:
754 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,0,2]
757 ; AVX-LABEL: combine_nested_undef_test9:
759 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,0,2]
761 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
762 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
766 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
767 ; SSE-LABEL: combine_nested_undef_test10:
769 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,0]
772 ; AVX-LABEL: combine_nested_undef_test10:
774 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,1,0]
776 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
777 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
781 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
782 ; SSE-LABEL: combine_nested_undef_test11:
784 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,1]
787 ; AVX-LABEL: combine_nested_undef_test11:
789 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,2,1]
791 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
792 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
796 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
797 ; SSE-LABEL: combine_nested_undef_test12:
799 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
802 ; AVX1-LABEL: combine_nested_undef_test12:
804 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
807 ; AVX2-LABEL: combine_nested_undef_test12:
809 ; AVX2-NEXT: vbroadcastss %xmm0, %xmm0
811 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
812 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
816 ; The following pair of shuffles is folded into vector %A.
817 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
818 ; ALL-LABEL: combine_nested_undef_test13:
821 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
822 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
826 ; The following pair of shuffles is folded into vector %B.
827 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
828 ; SSE-LABEL: combine_nested_undef_test14:
830 ; SSE-NEXT: movaps %xmm1, %xmm0
833 ; AVX-LABEL: combine_nested_undef_test14:
835 ; AVX-NEXT: vmovaps %xmm1, %xmm0
837 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
838 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
843 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
845 ; FIXME: Many of these already don't make sense, and the rest should stop
846 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
849 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
850 ; SSE-LABEL: combine_nested_undef_test15:
852 ; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
853 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
854 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
857 ; AVX-LABEL: combine_nested_undef_test15:
859 ; AVX-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
860 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
861 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
863 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
864 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
868 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
869 ; SSE2-LABEL: combine_nested_undef_test16:
871 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
872 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,2,0,3]
875 ; SSSE3-LABEL: combine_nested_undef_test16:
877 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
878 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,2,0,3]
881 ; SSE41-LABEL: combine_nested_undef_test16:
883 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
884 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
887 ; AVX1-LABEL: combine_nested_undef_test16:
889 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
890 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
893 ; AVX2-LABEL: combine_nested_undef_test16:
895 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
896 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
898 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
899 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
903 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
904 ; SSE-LABEL: combine_nested_undef_test17:
906 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
907 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
908 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
911 ; AVX-LABEL: combine_nested_undef_test17:
913 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
914 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
915 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
917 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
918 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
922 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
923 ; SSE-LABEL: combine_nested_undef_test18:
925 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
928 ; AVX-LABEL: combine_nested_undef_test18:
930 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
932 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
933 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
937 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
938 ; SSE-LABEL: combine_nested_undef_test19:
940 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
941 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
942 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
945 ; AVX-LABEL: combine_nested_undef_test19:
947 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
948 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
949 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
951 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
952 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
956 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
957 ; SSE-LABEL: combine_nested_undef_test20:
959 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
960 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
963 ; AVX-LABEL: combine_nested_undef_test20:
965 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
966 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
968 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
969 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
973 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
974 ; SSE-LABEL: combine_nested_undef_test21:
976 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
977 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
978 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
981 ; AVX-LABEL: combine_nested_undef_test21:
983 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
984 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
985 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
987 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
988 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
993 ; Test that we correctly combine shuffles according to rule
994 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
996 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
997 ; SSE-LABEL: combine_nested_undef_test22:
999 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1002 ; AVX-LABEL: combine_nested_undef_test22:
1004 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1006 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1007 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1011 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1012 ; SSE-LABEL: combine_nested_undef_test23:
1014 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1017 ; AVX-LABEL: combine_nested_undef_test23:
1019 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1021 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1022 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1026 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1027 ; SSE-LABEL: combine_nested_undef_test24:
1029 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,0]
1032 ; AVX-LABEL: combine_nested_undef_test24:
1034 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,0]
1036 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1037 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1041 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1042 ; SSE-LABEL: combine_nested_undef_test25:
1044 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1047 ; AVX-LABEL: combine_nested_undef_test25:
1049 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1051 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1052 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1056 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1057 ; SSE-LABEL: combine_nested_undef_test26:
1059 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
1062 ; AVX-LABEL: combine_nested_undef_test26:
1064 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
1066 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1067 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1071 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1072 ; SSE-LABEL: combine_nested_undef_test27:
1074 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1077 ; AVX-LABEL: combine_nested_undef_test27:
1079 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1081 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1082 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1086 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1087 ; SSE-LABEL: combine_nested_undef_test28:
1089 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1092 ; AVX-LABEL: combine_nested_undef_test28:
1094 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1096 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1097 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1101 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1102 ; SSE2-LABEL: combine_test1:
1104 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1105 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1106 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1107 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1110 ; SSSE3-LABEL: combine_test1:
1112 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1115 ; SSE41-LABEL: combine_test1:
1117 ; SSE41-NEXT: movaps %xmm1, %xmm0
1120 ; AVX-LABEL: combine_test1:
1122 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1124 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1125 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1129 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1130 ; SSE2-LABEL: combine_test2:
1132 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1133 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1134 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1135 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1138 ; SSSE3-LABEL: combine_test2:
1140 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1141 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1142 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1143 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1146 ; SSE41-LABEL: combine_test2:
1148 ; SSE41-NEXT: movss %xmm0, %xmm1
1149 ; SSE41-NEXT: movaps %xmm1, %xmm0
1152 ; AVX-LABEL: combine_test2:
1154 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
1156 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1157 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1161 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1162 ; SSE-LABEL: combine_test3:
1164 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1167 ; AVX-LABEL: combine_test3:
1169 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1171 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1172 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1176 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1177 ; SSE-LABEL: combine_test4:
1179 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1182 ; AVX-LABEL: combine_test4:
1184 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1186 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1187 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1191 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1192 ; SSE2-LABEL: combine_test5:
1194 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1195 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1196 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
1197 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
1200 ; SSSE3-LABEL: combine_test5:
1202 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1203 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1204 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
1205 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
1208 ; SSE41-LABEL: combine_test5:
1210 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1213 ; AVX-LABEL: combine_test5:
1215 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1217 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1218 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1222 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1223 ; SSE2-LABEL: combine_test6:
1225 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1226 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1227 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1228 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1231 ; SSSE3-LABEL: combine_test6:
1233 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1236 ; SSE41-LABEL: combine_test6:
1238 ; SSE41-NEXT: movaps %xmm1, %xmm0
1241 ; AVX-LABEL: combine_test6:
1243 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1245 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1246 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1250 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1251 ; SSE2-LABEL: combine_test7:
1253 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1254 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1255 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1256 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1259 ; SSSE3-LABEL: combine_test7:
1261 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1262 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1263 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1264 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1267 ; SSE41-LABEL: combine_test7:
1269 ; SSE41-NEXT: movss %xmm0, %xmm1
1270 ; SSE41-NEXT: movaps %xmm1, %xmm0
1273 ; AVX-LABEL: combine_test7:
1275 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
1277 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1278 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1282 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1283 ; SSE-LABEL: combine_test8:
1285 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1288 ; AVX-LABEL: combine_test8:
1290 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1292 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1293 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1297 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1298 ; SSE-LABEL: combine_test9:
1300 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1303 ; AVX-LABEL: combine_test9:
1305 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1307 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1308 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1312 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1313 ; SSE2-LABEL: combine_test10:
1315 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1316 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1317 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
1318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
1321 ; SSSE3-LABEL: combine_test10:
1323 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1324 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1325 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
1326 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
1329 ; SSE41-LABEL: combine_test10:
1331 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1334 ; AVX1-LABEL: combine_test10:
1336 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1339 ; AVX2-LABEL: combine_test10:
1341 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1343 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1344 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1348 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1349 ; ALL-LABEL: combine_test11:
1352 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1353 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1357 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1358 ; SSE2-LABEL: combine_test12:
1360 ; SSE2-NEXT: movss %xmm0, %xmm1
1361 ; SSE2-NEXT: movss %xmm0, %xmm1
1362 ; SSE2-NEXT: movaps %xmm1, %xmm0
1365 ; SSSE3-LABEL: combine_test12:
1367 ; SSSE3-NEXT: movss %xmm0, %xmm1
1368 ; SSSE3-NEXT: movss %xmm0, %xmm1
1369 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1372 ; SSE41-LABEL: combine_test12:
1374 ; SSE41-NEXT: movss %xmm0, %xmm1
1375 ; SSE41-NEXT: movaps %xmm1, %xmm0
1378 ; AVX-LABEL: combine_test12:
1380 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
1382 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1383 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1387 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1388 ; SSE-LABEL: combine_test13:
1390 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1393 ; AVX-LABEL: combine_test13:
1395 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1397 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1398 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1402 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1403 ; SSE-LABEL: combine_test14:
1405 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
1406 ; SSE-NEXT: movaps %xmm1, %xmm0
1409 ; AVX-LABEL: combine_test14:
1411 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1413 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1414 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1418 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1419 ; SSE2-LABEL: combine_test15:
1421 ; SSE2-NEXT: movaps %xmm0, %xmm2
1422 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1423 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1424 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1425 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1428 ; SSSE3-LABEL: combine_test15:
1430 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1431 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1432 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1433 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1434 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1437 ; SSE41-LABEL: combine_test15:
1439 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1442 ; AVX-LABEL: combine_test15:
1444 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1446 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1447 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1451 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1452 ; ALL-LABEL: combine_test16:
1455 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1456 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1460 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1461 ; SSE2-LABEL: combine_test17:
1463 ; SSE2-NEXT: movss %xmm0, %xmm1
1464 ; SSE2-NEXT: movss %xmm0, %xmm1
1465 ; SSE2-NEXT: movaps %xmm1, %xmm0
1468 ; SSSE3-LABEL: combine_test17:
1470 ; SSSE3-NEXT: movss %xmm0, %xmm1
1471 ; SSSE3-NEXT: movss %xmm0, %xmm1
1472 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1475 ; SSE41-LABEL: combine_test17:
1477 ; SSE41-NEXT: movss %xmm0, %xmm1
1478 ; SSE41-NEXT: movaps %xmm1, %xmm0
1481 ; AVX-LABEL: combine_test17:
1483 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
1485 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1486 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1490 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1491 ; SSE-LABEL: combine_test18:
1493 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1496 ; AVX-LABEL: combine_test18:
1498 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1500 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1501 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1505 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1506 ; SSE-LABEL: combine_test19:
1508 ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
1509 ; SSE-NEXT: movaps %xmm1, %xmm0
1512 ; AVX-LABEL: combine_test19:
1514 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1516 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1517 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1521 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1522 ; SSE2-LABEL: combine_test20:
1524 ; SSE2-NEXT: movaps %xmm0, %xmm2
1525 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1526 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1527 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1528 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1531 ; SSSE3-LABEL: combine_test20:
1533 ; SSSE3-NEXT: movaps %xmm0, %xmm2
1534 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm1[0,0]
1535 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
1536 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,0]
1537 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
1540 ; SSE41-LABEL: combine_test20:
1542 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1545 ; AVX1-LABEL: combine_test20:
1547 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1550 ; AVX2-LABEL: combine_test20:
1552 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1554 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1555 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1560 ; Check some negative cases.
1561 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1563 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1564 ; SSE2-LABEL: combine_test1b:
1566 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1567 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1568 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1569 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0]
1570 ; SSE2-NEXT: movaps %xmm1, %xmm0
1573 ; SSSE3-LABEL: combine_test1b:
1575 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1576 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1577 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1578 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0]
1579 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1582 ; SSE41-LABEL: combine_test1b:
1584 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1585 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1586 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0]
1587 ; SSE41-NEXT: movaps %xmm1, %xmm0
1590 ; AVX-LABEL: combine_test1b:
1592 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1593 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1594 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,0]
1596 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1597 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1601 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1602 ; SSE2-LABEL: combine_test2b:
1604 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1605 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1606 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1607 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1610 ; SSSE3-LABEL: combine_test2b:
1612 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1613 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1614 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1615 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1618 ; SSE41-LABEL: combine_test2b:
1620 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1621 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1622 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1625 ; AVX-LABEL: combine_test2b:
1627 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1628 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
1629 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1631 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1632 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1636 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1637 ; SSE-LABEL: combine_test3b:
1639 ; SSE-NEXT: movaps %xmm1, %xmm2
1640 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1641 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1642 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1643 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1646 ; AVX-LABEL: combine_test3b:
1648 ; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,0],xmm0[3,0]
1649 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,2]
1650 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[3,3]
1651 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1653 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1654 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1658 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1659 ; SSE2-LABEL: combine_test4b:
1661 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1662 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1663 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1664 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[0,2]
1665 ; SSE2-NEXT: movaps %xmm1, %xmm0
1668 ; SSSE3-LABEL: combine_test4b:
1670 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1671 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1672 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1673 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[0,2]
1674 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1677 ; SSE41-LABEL: combine_test4b:
1679 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1680 ; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1681 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[0,2]
1682 ; SSE41-NEXT: movaps %xmm1, %xmm0
1685 ; AVX-LABEL: combine_test4b:
1687 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1688 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
1689 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,1],xmm0[0,2]
1691 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1692 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1697 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1699 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1700 ; SSE2-LABEL: combine_test1c:
1702 ; SSE2-NEXT: movl (%rdi), %eax
1703 ; SSE2-NEXT: movd %eax, %xmm0
1704 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx
1705 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
1706 ; SSE2-NEXT: movzbl %ah, %eax
1707 ; SSE2-NEXT: pinsrw $2, %eax, %xmm0
1708 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm0
1709 ; SSE2-NEXT: shrl $8, %ecx
1710 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm0
1711 ; SSE2-NEXT: movl (%rsi), %eax
1712 ; SSE2-NEXT: movd %eax, %xmm1
1713 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx
1714 ; SSE2-NEXT: pinsrw $0, %eax, %xmm1
1715 ; SSE2-NEXT: movzbl %ah, %eax
1716 ; SSE2-NEXT: pinsrw $2, %eax, %xmm1
1717 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm1
1718 ; SSE2-NEXT: shrl $8, %ecx
1719 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm1
1720 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
1721 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1722 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
1723 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
1726 ; SSSE3-LABEL: combine_test1c:
1728 ; SSSE3-NEXT: movd (%rdi), %xmm0
1729 ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,128,128,128,1,128,128,128,2,128,128,128,3,128,128,128]
1730 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
1731 ; SSSE3-NEXT: movd (%rsi), %xmm2
1732 ; SSSE3-NEXT: pshufb %xmm1, %xmm2
1733 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
1734 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
1735 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[3,0]
1736 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2]
1739 ; SSE41-LABEL: combine_test1c:
1741 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm1
1742 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm0
1743 ; SSE41-NEXT: movss %xmm1, %xmm0
1746 ; AVX-LABEL: combine_test1c:
1748 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1749 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1750 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
1752 %A = load <4 x i8>* %a
1753 %B = load <4 x i8>* %b
1754 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1755 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1759 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1760 ; SSE2-LABEL: combine_test2c:
1762 ; SSE2-NEXT: movl (%rdi), %eax
1763 ; SSE2-NEXT: movd %eax, %xmm0
1764 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx
1765 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
1766 ; SSE2-NEXT: movzbl %ah, %eax
1767 ; SSE2-NEXT: pinsrw $2, %eax, %xmm0
1768 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm0
1769 ; SSE2-NEXT: shrl $8, %ecx
1770 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm0
1771 ; SSE2-NEXT: movl (%rsi), %eax
1772 ; SSE2-NEXT: movd %eax, %xmm1
1773 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx
1774 ; SSE2-NEXT: pinsrw $0, %eax, %xmm1
1775 ; SSE2-NEXT: movzbl %ah, %eax
1776 ; SSE2-NEXT: pinsrw $2, %eax, %xmm1
1777 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm1
1778 ; SSE2-NEXT: shrl $8, %ecx
1779 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm1
1780 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1783 ; SSSE3-LABEL: combine_test2c:
1785 ; SSSE3-NEXT: movd (%rdi), %xmm0
1786 ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,128,128,128,1,128,128,128,2,128,128,128,3,128,128,128]
1787 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
1788 ; SSSE3-NEXT: movd (%rsi), %xmm2
1789 ; SSSE3-NEXT: pshufb %xmm1, %xmm2
1790 ; SSSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
1793 ; SSE41-LABEL: combine_test2c:
1795 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1796 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1797 ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1800 ; AVX-LABEL: combine_test2c:
1802 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1803 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1804 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1806 %A = load <4 x i8>* %a
1807 %B = load <4 x i8>* %b
1808 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1809 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1813 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1814 ; SSE2-LABEL: combine_test3c:
1816 ; SSE2-NEXT: movl (%rdi), %eax
1817 ; SSE2-NEXT: movd %eax, %xmm0
1818 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx
1819 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
1820 ; SSE2-NEXT: movzbl %ah, %eax
1821 ; SSE2-NEXT: pinsrw $2, %eax, %xmm0
1822 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm0
1823 ; SSE2-NEXT: shrl $8, %ecx
1824 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm0
1825 ; SSE2-NEXT: movl (%rsi), %eax
1826 ; SSE2-NEXT: movd %eax, %xmm1
1827 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx
1828 ; SSE2-NEXT: pinsrw $0, %eax, %xmm1
1829 ; SSE2-NEXT: movzbl %ah, %eax
1830 ; SSE2-NEXT: pinsrw $2, %eax, %xmm1
1831 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm1
1832 ; SSE2-NEXT: shrl $8, %ecx
1833 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm1
1834 ; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1837 ; SSSE3-LABEL: combine_test3c:
1839 ; SSSE3-NEXT: movd (%rdi), %xmm0
1840 ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,128,128,128,1,128,128,128,2,128,128,128,3,128,128,128]
1841 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
1842 ; SSSE3-NEXT: movd (%rsi), %xmm2
1843 ; SSSE3-NEXT: pshufb %xmm1, %xmm2
1844 ; SSSE3-NEXT: movhlps {{.*#+}} xmm0 = xmm2[1],xmm0[1]
1847 ; SSE41-LABEL: combine_test3c:
1849 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1850 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1851 ; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1854 ; AVX-LABEL: combine_test3c:
1856 ; AVX-NEXT: vpmovzxbd (%rdi), %xmm0
1857 ; AVX-NEXT: vpmovzxbd (%rsi), %xmm1
1858 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1860 %A = load <4 x i8>* %a
1861 %B = load <4 x i8>* %b
1862 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1863 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1867 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1868 ; SSE2-LABEL: combine_test4c:
1870 ; SSE2-NEXT: movl (%rdi), %eax
1871 ; SSE2-NEXT: movd %eax, %xmm0
1872 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx
1873 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
1874 ; SSE2-NEXT: movzbl %ah, %eax
1875 ; SSE2-NEXT: pinsrw $2, %eax, %xmm0
1876 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm0
1877 ; SSE2-NEXT: shrl $8, %ecx
1878 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm0
1879 ; SSE2-NEXT: movl (%rsi), %eax
1880 ; SSE2-NEXT: movd %eax, %xmm1
1881 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx
1882 ; SSE2-NEXT: pinsrw $0, %eax, %xmm1
1883 ; SSE2-NEXT: movzbl %ah, %eax
1884 ; SSE2-NEXT: pinsrw $2, %eax, %xmm1
1885 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm1
1886 ; SSE2-NEXT: shrl $8, %ecx
1887 ; SSE2-NEXT: pinsrw $6, %ecx, %xmm1
1888 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
1889 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1890 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
1891 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
1894 ; SSSE3-LABEL: combine_test4c:
1896 ; SSSE3-NEXT: movd (%rdi), %xmm0
1897 ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,128,128,128,1,128,128,128,2,128,128,128,3,128,128,128]
1898 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
1899 ; SSSE3-NEXT: movd (%rsi), %xmm2
1900 ; SSSE3-NEXT: pshufb %xmm1, %xmm2
1901 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[0,2]
1902 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
1903 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]
1904 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
1907 ; SSE41-LABEL: combine_test4c:
1909 ; SSE41-NEXT: pmovzxbd (%rdi), %xmm0
1910 ; SSE41-NEXT: pmovzxbd (%rsi), %xmm1
1911 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1914 ; AVX1-LABEL: combine_test4c:
1916 ; AVX1-NEXT: vpmovzxbd (%rdi), %xmm0
1917 ; AVX1-NEXT: vpmovzxbd (%rsi), %xmm1
1918 ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1921 ; AVX2-LABEL: combine_test4c:
1923 ; AVX2-NEXT: vpmovzxbd (%rdi), %xmm0
1924 ; AVX2-NEXT: vpmovzxbd (%rsi), %xmm1
1925 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1927 %A = load <4 x i8>* %a
1928 %B = load <4 x i8>* %b
1929 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1930 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1935 ; The following test cases are generated from this C++ code
1937 ;__m128 blend_01(__m128 a, __m128 b)
1940 ; s = _mm_blend_ps( s, b, 1<<0 );
1941 ; s = _mm_blend_ps( s, b, 1<<1 );
1945 ;__m128 blend_02(__m128 a, __m128 b)
1948 ; s = _mm_blend_ps( s, b, 1<<0 );
1949 ; s = _mm_blend_ps( s, b, 1<<2 );
1953 ;__m128 blend_123(__m128 a, __m128 b)
1956 ; s = _mm_blend_ps( s, b, 1<<1 );
1957 ; s = _mm_blend_ps( s, b, 1<<2 );
1958 ; s = _mm_blend_ps( s, b, 1<<3 );
1962 ; Ideally, we should collapse the following shuffles into a single one.
1964 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1965 ; SSE2-LABEL: combine_blend_01:
1967 ; SSE2-NEXT: movss %xmm1, %xmm0
1968 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1969 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1970 ; SSE2-NEXT: movaps %xmm1, %xmm0
1973 ; SSSE3-LABEL: combine_blend_01:
1975 ; SSSE3-NEXT: movss %xmm1, %xmm0
1976 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
1977 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
1978 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1981 ; SSE41-LABEL: combine_blend_01:
1983 ; SSE41-NEXT: movsd %xmm1, %xmm0
1986 ; AVX-LABEL: combine_blend_01:
1988 ; AVX-NEXT: vmovsd %xmm1, %xmm0, %xmm0
1990 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1991 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1992 ret <4 x float> %shuffle6
1995 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1996 ; SSE2-LABEL: combine_blend_02:
1998 ; SSE2-NEXT: movss %xmm1, %xmm0
1999 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2000 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2003 ; SSSE3-LABEL: combine_blend_02:
2005 ; SSSE3-NEXT: movss %xmm1, %xmm0
2006 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
2007 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2010 ; SSE41-LABEL: combine_blend_02:
2012 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2015 ; AVX-LABEL: combine_blend_02:
2017 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2019 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2020 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2021 ret <4 x float> %shuffle6
2024 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2025 ; SSE2-LABEL: combine_blend_123:
2027 ; SSE2-NEXT: movaps %xmm1, %xmm2
2028 ; SSE2-NEXT: movss %xmm0, %xmm2
2029 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
2030 ; SSE2-NEXT: movaps %xmm2, %xmm0
2033 ; SSSE3-LABEL: combine_blend_123:
2035 ; SSSE3-NEXT: movaps %xmm1, %xmm2
2036 ; SSSE3-NEXT: movss %xmm0, %xmm2
2037 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
2038 ; SSSE3-NEXT: movaps %xmm2, %xmm0
2041 ; SSE41-LABEL: combine_blend_123:
2043 ; SSE41-NEXT: movss %xmm0, %xmm1
2044 ; SSE41-NEXT: movaps %xmm1, %xmm0
2047 ; AVX-LABEL: combine_blend_123:
2049 ; AVX-NEXT: vmovss %xmm0, %xmm1, %xmm0
2051 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2052 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2053 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2054 ret <4 x float> %shuffle12
2057 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2058 ; SSE-LABEL: combine_test_movhl_1:
2060 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2063 ; AVX-LABEL: combine_test_movhl_1:
2065 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2067 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2068 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2072 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2073 ; SSE-LABEL: combine_test_movhl_2:
2075 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2078 ; AVX-LABEL: combine_test_movhl_2:
2080 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2082 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2083 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2087 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2088 ; SSE-LABEL: combine_test_movhl_3:
2090 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2093 ; AVX-LABEL: combine_test_movhl_3:
2095 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2097 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2098 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>