1 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2 ; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3 ; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 -x86-experimental-vector-shuffle-legality | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7 ; Verify that the DAG combiner correctly folds bitwise operations across
8 ; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9 ; basic and always-safe patterns. Also test that the DAG combiner will combine
10 ; target-specific shuffle instructions where reasonable.
12 target triple = "x86_64-unknown-unknown"
14 declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15 declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16 declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18 define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19 ; ALL-LABEL: combine_pshufd1:
20 ; ALL: # BB#0: # %entry
23 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28 define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29 ; ALL-LABEL: combine_pshufd2:
30 ; ALL: # BB#0: # %entry
33 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34 %b.cast = bitcast <4 x i32> %b to <8 x i16>
35 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36 %c.cast = bitcast <8 x i16> %c to <4 x i32>
37 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41 define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42 ; ALL-LABEL: combine_pshufd3:
43 ; ALL: # BB#0: # %entry
46 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47 %b.cast = bitcast <4 x i32> %b to <8 x i16>
48 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49 %c.cast = bitcast <8 x i16> %c to <4 x i32>
50 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54 define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55 ; SSE-LABEL: combine_pshufd4:
56 ; SSE: # BB#0: # %entry
57 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60 ; AVX-LABEL: combine_pshufd4:
61 ; AVX: # BB#0: # %entry
62 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66 %b.cast = bitcast <4 x i32> %b to <8 x i16>
67 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68 %c.cast = bitcast <8 x i16> %c to <4 x i32>
69 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73 define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74 ; SSE-LABEL: combine_pshufd5:
75 ; SSE: # BB#0: # %entry
76 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79 ; AVX-LABEL: combine_pshufd5:
80 ; AVX: # BB#0: # %entry
81 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85 %b.cast = bitcast <4 x i32> %b to <8 x i16>
86 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87 %c.cast = bitcast <8 x i16> %c to <4 x i32>
88 %d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92 define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93 ; SSE-LABEL: combine_pshufd6:
94 ; SSE: # BB#0: # %entry
95 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98 ; AVX-LABEL: combine_pshufd6:
99 ; AVX: # BB#0: # %entry
100 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103 %b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104 %c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108 define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109 ; ALL-LABEL: combine_pshuflw1:
110 ; ALL: # BB#0: # %entry
113 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118 define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119 ; ALL-LABEL: combine_pshuflw2:
120 ; ALL: # BB#0: # %entry
123 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129 define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130 ; SSE-LABEL: combine_pshuflw3:
131 ; SSE: # BB#0: # %entry
132 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135 ; AVX-LABEL: combine_pshuflw3:
136 ; AVX: # BB#0: # %entry
137 ; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140 %b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141 %c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142 %d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146 define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147 ; SSE-LABEL: combine_pshufhw1:
148 ; SSE: # BB#0: # %entry
149 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152 ; AVX-LABEL: combine_pshufhw1:
153 ; AVX: # BB#0: # %entry
154 ; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157 %b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158 %c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159 %d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163 define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; SSE-LABEL: combine_bitwise_ops_test1:
166 ; SSE-NEXT: pand %xmm1, %xmm0
167 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170 ; AVX-LABEL: combine_bitwise_ops_test1:
172 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177 %and = and <4 x i32> %shuf1, %shuf2
181 define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182 ; SSE-LABEL: combine_bitwise_ops_test2:
184 ; SSE-NEXT: por %xmm1, %xmm0
185 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188 ; AVX-LABEL: combine_bitwise_ops_test2:
190 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195 %or = or <4 x i32> %shuf1, %shuf2
199 define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200 ; SSE-LABEL: combine_bitwise_ops_test3:
202 ; SSE-NEXT: pxor %xmm1, %xmm0
203 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206 ; AVX-LABEL: combine_bitwise_ops_test3:
208 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213 %xor = xor <4 x i32> %shuf1, %shuf2
217 define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218 ; SSE-LABEL: combine_bitwise_ops_test4:
220 ; SSE-NEXT: pand %xmm1, %xmm0
221 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224 ; AVX-LABEL: combine_bitwise_ops_test4:
226 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231 %and = and <4 x i32> %shuf1, %shuf2
235 define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236 ; SSE-LABEL: combine_bitwise_ops_test5:
238 ; SSE-NEXT: por %xmm1, %xmm0
239 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242 ; AVX-LABEL: combine_bitwise_ops_test5:
244 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249 %or = or <4 x i32> %shuf1, %shuf2
253 define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254 ; SSE-LABEL: combine_bitwise_ops_test6:
256 ; SSE-NEXT: pxor %xmm1, %xmm0
257 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260 ; AVX-LABEL: combine_bitwise_ops_test6:
262 ; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267 %xor = xor <4 x i32> %shuf1, %shuf2
272 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273 ; are not performing a swizzle operations.
275 define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276 ; SSE2-LABEL: combine_bitwise_ops_test1b:
278 ; SSE2-NEXT: andps %xmm1, %xmm0
279 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
283 ; SSSE3-LABEL: combine_bitwise_ops_test1b:
285 ; SSSE3-NEXT: andps %xmm1, %xmm0
286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
290 ; SSE41-LABEL: combine_bitwise_ops_test1b:
292 ; SSE41-NEXT: pand %xmm1, %xmm0
293 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
296 ; AVX1-LABEL: combine_bitwise_ops_test1b:
298 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
299 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
302 ; AVX2-LABEL: combine_bitwise_ops_test1b:
304 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
305 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
307 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
308 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
309 %and = and <4 x i32> %shuf1, %shuf2
313 define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314 ; SSE2-LABEL: combine_bitwise_ops_test2b:
316 ; SSE2-NEXT: orps %xmm1, %xmm0
317 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
318 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
321 ; SSSE3-LABEL: combine_bitwise_ops_test2b:
323 ; SSSE3-NEXT: orps %xmm1, %xmm0
324 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
325 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
328 ; SSE41-LABEL: combine_bitwise_ops_test2b:
330 ; SSE41-NEXT: por %xmm1, %xmm0
331 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
334 ; AVX1-LABEL: combine_bitwise_ops_test2b:
336 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
337 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
340 ; AVX2-LABEL: combine_bitwise_ops_test2b:
342 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
343 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
345 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
346 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
347 %or = or <4 x i32> %shuf1, %shuf2
351 define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
352 ; SSE2-LABEL: combine_bitwise_ops_test3b:
354 ; SSE2-NEXT: xorps %xmm1, %xmm0
355 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
358 ; SSSE3-LABEL: combine_bitwise_ops_test3b:
360 ; SSSE3-NEXT: xorps %xmm1, %xmm0
361 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
364 ; SSE41-LABEL: combine_bitwise_ops_test3b:
366 ; SSE41-NEXT: pxor %xmm1, %xmm0
367 ; SSE41-NEXT: pxor %xmm1, %xmm1
368 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
371 ; AVX1-LABEL: combine_bitwise_ops_test3b:
373 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
374 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
375 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
378 ; AVX2-LABEL: combine_bitwise_ops_test3b:
380 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
381 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
382 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
384 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
385 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
386 %xor = xor <4 x i32> %shuf1, %shuf2
390 define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
391 ; SSE2-LABEL: combine_bitwise_ops_test4b:
393 ; SSE2-NEXT: andps %xmm1, %xmm0
394 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
395 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
396 ; SSE2-NEXT: movaps %xmm2, %xmm0
399 ; SSSE3-LABEL: combine_bitwise_ops_test4b:
401 ; SSSE3-NEXT: andps %xmm1, %xmm0
402 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
403 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
404 ; SSSE3-NEXT: movaps %xmm2, %xmm0
407 ; SSE41-LABEL: combine_bitwise_ops_test4b:
409 ; SSE41-NEXT: pand %xmm1, %xmm0
410 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
413 ; AVX1-LABEL: combine_bitwise_ops_test4b:
415 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
416 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
419 ; AVX2-LABEL: combine_bitwise_ops_test4b:
421 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
422 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
424 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
425 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
426 %and = and <4 x i32> %shuf1, %shuf2
430 define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
431 ; SSE2-LABEL: combine_bitwise_ops_test5b:
433 ; SSE2-NEXT: orps %xmm1, %xmm0
434 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
435 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
436 ; SSE2-NEXT: movaps %xmm2, %xmm0
439 ; SSSE3-LABEL: combine_bitwise_ops_test5b:
441 ; SSSE3-NEXT: orps %xmm1, %xmm0
442 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
443 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
444 ; SSSE3-NEXT: movaps %xmm2, %xmm0
447 ; SSE41-LABEL: combine_bitwise_ops_test5b:
449 ; SSE41-NEXT: por %xmm1, %xmm0
450 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
453 ; AVX1-LABEL: combine_bitwise_ops_test5b:
455 ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
456 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
459 ; AVX2-LABEL: combine_bitwise_ops_test5b:
461 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
462 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
464 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
465 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
466 %or = or <4 x i32> %shuf1, %shuf2
470 define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
471 ; SSE2-LABEL: combine_bitwise_ops_test6b:
473 ; SSE2-NEXT: xorps %xmm1, %xmm0
474 ; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
477 ; SSSE3-LABEL: combine_bitwise_ops_test6b:
479 ; SSSE3-NEXT: xorps %xmm1, %xmm0
480 ; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
483 ; SSE41-LABEL: combine_bitwise_ops_test6b:
485 ; SSE41-NEXT: pxor %xmm1, %xmm0
486 ; SSE41-NEXT: pxor %xmm1, %xmm1
487 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
490 ; AVX1-LABEL: combine_bitwise_ops_test6b:
492 ; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
493 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
494 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
497 ; AVX2-LABEL: combine_bitwise_ops_test6b:
499 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
500 ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
501 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
503 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
504 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
505 %xor = xor <4 x i32> %shuf1, %shuf2
509 define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
510 ; SSE-LABEL: combine_bitwise_ops_test1c:
512 ; SSE-NEXT: andps %xmm1, %xmm0
513 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
516 ; AVX-LABEL: combine_bitwise_ops_test1c:
518 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
519 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
521 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
522 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
523 %and = and <4 x i32> %shuf1, %shuf2
527 define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
528 ; SSE-LABEL: combine_bitwise_ops_test2c:
530 ; SSE-NEXT: orps %xmm1, %xmm0
531 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
534 ; AVX-LABEL: combine_bitwise_ops_test2c:
536 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
537 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
539 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
540 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
541 %or = or <4 x i32> %shuf1, %shuf2
545 define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
546 ; SSE2-LABEL: combine_bitwise_ops_test3c:
548 ; SSE2-NEXT: xorps %xmm1, %xmm0
549 ; SSE2-NEXT: xorps %xmm1, %xmm1
550 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
553 ; SSSE3-LABEL: combine_bitwise_ops_test3c:
555 ; SSSE3-NEXT: xorps %xmm1, %xmm0
556 ; SSSE3-NEXT: xorps %xmm1, %xmm1
557 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
560 ; SSE41-LABEL: combine_bitwise_ops_test3c:
562 ; SSE41-NEXT: xorps %xmm1, %xmm0
563 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
566 ; AVX-LABEL: combine_bitwise_ops_test3c:
568 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
569 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
571 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
572 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
573 %xor = xor <4 x i32> %shuf1, %shuf2
577 define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
578 ; SSE-LABEL: combine_bitwise_ops_test4c:
580 ; SSE-NEXT: andps %xmm1, %xmm0
581 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
582 ; SSE-NEXT: movaps %xmm2, %xmm0
585 ; AVX-LABEL: combine_bitwise_ops_test4c:
587 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
588 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
590 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
591 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
592 %and = and <4 x i32> %shuf1, %shuf2
596 define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
597 ; SSE-LABEL: combine_bitwise_ops_test5c:
599 ; SSE-NEXT: orps %xmm1, %xmm0
600 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
601 ; SSE-NEXT: movaps %xmm2, %xmm0
604 ; AVX-LABEL: combine_bitwise_ops_test5c:
606 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
607 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
609 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
610 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
611 %or = or <4 x i32> %shuf1, %shuf2
615 define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
616 ; SSE-LABEL: combine_bitwise_ops_test6c:
618 ; SSE-NEXT: xorps %xmm1, %xmm0
619 ; SSE-NEXT: xorps %xmm1, %xmm1
620 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
621 ; SSE-NEXT: movaps %xmm1, %xmm0
624 ; AVX-LABEL: combine_bitwise_ops_test6c:
626 ; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
627 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
628 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
630 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
632 %xor = xor <4 x i32> %shuf1, %shuf2
636 define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
637 ; SSE-LABEL: combine_nested_undef_test1:
639 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
642 ; AVX-LABEL: combine_nested_undef_test1:
644 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
646 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
647 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
651 define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
652 ; SSE-LABEL: combine_nested_undef_test2:
654 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
657 ; AVX-LABEL: combine_nested_undef_test2:
659 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
661 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
662 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
666 define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
667 ; SSE-LABEL: combine_nested_undef_test3:
669 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
672 ; AVX-LABEL: combine_nested_undef_test3:
674 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
676 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
677 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
681 define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
682 ; SSE-LABEL: combine_nested_undef_test4:
684 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
687 ; AVX1-LABEL: combine_nested_undef_test4:
689 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
692 ; AVX2-LABEL: combine_nested_undef_test4:
694 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
696 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
697 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
701 define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
702 ; SSE-LABEL: combine_nested_undef_test5:
704 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
707 ; AVX-LABEL: combine_nested_undef_test5:
709 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
711 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
712 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
716 define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
717 ; SSE-LABEL: combine_nested_undef_test6:
719 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
722 ; AVX-LABEL: combine_nested_undef_test6:
724 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
726 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
727 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
731 define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
732 ; SSE-LABEL: combine_nested_undef_test7:
734 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
737 ; AVX-LABEL: combine_nested_undef_test7:
739 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
741 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
742 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
746 define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
747 ; SSE-LABEL: combine_nested_undef_test8:
749 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
752 ; AVX-LABEL: combine_nested_undef_test8:
754 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
756 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
757 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
761 define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
762 ; SSE-LABEL: combine_nested_undef_test9:
764 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
767 ; AVX-LABEL: combine_nested_undef_test9:
769 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
771 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
772 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
776 define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
777 ; SSE-LABEL: combine_nested_undef_test10:
779 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
782 ; AVX-LABEL: combine_nested_undef_test10:
784 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
786 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
787 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
791 define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
792 ; SSE-LABEL: combine_nested_undef_test11:
794 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
797 ; AVX-LABEL: combine_nested_undef_test11:
799 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
801 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
802 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
806 define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
807 ; SSE-LABEL: combine_nested_undef_test12:
809 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
812 ; AVX1-LABEL: combine_nested_undef_test12:
814 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
817 ; AVX2-LABEL: combine_nested_undef_test12:
819 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
821 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
822 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
826 ; The following pair of shuffles is folded into vector %A.
827 define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
828 ; ALL-LABEL: combine_nested_undef_test13:
831 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
832 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
836 ; The following pair of shuffles is folded into vector %B.
837 define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
838 ; SSE-LABEL: combine_nested_undef_test14:
840 ; SSE-NEXT: movaps %xmm1, %xmm0
843 ; AVX-LABEL: combine_nested_undef_test14:
845 ; AVX-NEXT: vmovaps %xmm1, %xmm0
847 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
848 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
853 ; Verify that we don't optimize the following cases. We expect more than one shuffle.
855 ; FIXME: Many of these already don't make sense, and the rest should stop
856 ; making sense with th enew vector shuffle lowering. Revisit at least testing for
859 define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
860 ; SSE-LABEL: combine_nested_undef_test15:
862 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
863 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
864 ; SSE-NEXT: movaps %xmm1, %xmm0
867 ; AVX-LABEL: combine_nested_undef_test15:
869 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
870 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[0,1]
872 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
873 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
877 define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
878 ; SSE-LABEL: combine_nested_undef_test16:
880 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
881 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
884 ; AVX-LABEL: combine_nested_undef_test16:
886 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[1,3]
887 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
889 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
890 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
894 define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
895 ; SSE-LABEL: combine_nested_undef_test17:
897 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
898 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
901 ; AVX-LABEL: combine_nested_undef_test17:
903 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
904 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
906 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
907 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
911 define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
912 ; SSE-LABEL: combine_nested_undef_test18:
914 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
917 ; AVX-LABEL: combine_nested_undef_test18:
919 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
921 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
922 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
926 define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
927 ; SSE-LABEL: combine_nested_undef_test19:
929 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
930 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[0,0]
931 ; SSE-NEXT: movaps %xmm1, %xmm0
934 ; AVX-LABEL: combine_nested_undef_test19:
936 ; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
937 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[0,0]
939 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
940 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
944 define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
945 ; SSE-LABEL: combine_nested_undef_test20:
947 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
948 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
949 ; SSE-NEXT: movaps %xmm1, %xmm0
952 ; AVX-LABEL: combine_nested_undef_test20:
954 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[2,3]
955 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
957 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
958 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
962 define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
963 ; SSE-LABEL: combine_nested_undef_test21:
965 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,1]
966 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
967 ; SSE-NEXT: movaps %xmm1, %xmm0
970 ; AVX-LABEL: combine_nested_undef_test21:
972 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[1,1]
973 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
975 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
976 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
981 ; Test that we correctly combine shuffles according to rule
982 ; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
984 define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
985 ; SSE-LABEL: combine_nested_undef_test22:
987 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
990 ; AVX-LABEL: combine_nested_undef_test22:
992 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
994 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
995 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
999 define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1000 ; SSE-LABEL: combine_nested_undef_test23:
1002 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1005 ; AVX-LABEL: combine_nested_undef_test23:
1007 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1009 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1010 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1014 define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1015 ; SSE-LABEL: combine_nested_undef_test24:
1017 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1020 ; AVX-LABEL: combine_nested_undef_test24:
1022 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1024 %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1025 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1029 define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1030 ; SSE-LABEL: combine_nested_undef_test25:
1032 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1035 ; AVX1-LABEL: combine_nested_undef_test25:
1037 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1040 ; AVX2-LABEL: combine_nested_undef_test25:
1042 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1044 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1045 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1049 define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1050 ; SSE-LABEL: combine_nested_undef_test26:
1052 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1055 ; AVX-LABEL: combine_nested_undef_test26:
1057 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1059 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1060 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1064 define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1065 ; SSE-LABEL: combine_nested_undef_test27:
1067 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1070 ; AVX1-LABEL: combine_nested_undef_test27:
1072 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1075 ; AVX2-LABEL: combine_nested_undef_test27:
1077 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1079 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1080 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1084 define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1085 ; SSE-LABEL: combine_nested_undef_test28:
1087 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1090 ; AVX-LABEL: combine_nested_undef_test28:
1092 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1094 %1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1095 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1099 define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1100 ; SSE-LABEL: combine_test1:
1102 ; SSE-NEXT: movaps %xmm1, %xmm0
1105 ; AVX-LABEL: combine_test1:
1107 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1109 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1110 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1114 define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1115 ; SSE2-LABEL: combine_test2:
1117 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1118 ; SSE2-NEXT: movaps %xmm1, %xmm0
1121 ; SSSE3-LABEL: combine_test2:
1123 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1124 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1127 ; SSE41-LABEL: combine_test2:
1129 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1132 ; AVX-LABEL: combine_test2:
1134 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1136 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1137 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1141 define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1142 ; SSE-LABEL: combine_test3:
1144 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1147 ; AVX-LABEL: combine_test3:
1149 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1151 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1152 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1156 define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1157 ; SSE-LABEL: combine_test4:
1159 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1160 ; SSE-NEXT: movapd %xmm1, %xmm0
1163 ; AVX-LABEL: combine_test4:
1165 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1167 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1168 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1172 define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1173 ; SSE2-LABEL: combine_test5:
1175 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1176 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1179 ; SSSE3-LABEL: combine_test5:
1181 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1182 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1185 ; SSE41-LABEL: combine_test5:
1187 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1190 ; AVX-LABEL: combine_test5:
1192 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1194 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1195 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1199 define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1200 ; SSE-LABEL: combine_test6:
1202 ; SSE-NEXT: movaps %xmm1, %xmm0
1205 ; AVX-LABEL: combine_test6:
1207 ; AVX-NEXT: vmovaps %xmm1, %xmm0
1209 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1210 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1214 define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1215 ; SSE2-LABEL: combine_test7:
1217 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1218 ; SSE2-NEXT: movaps %xmm1, %xmm0
1221 ; SSSE3-LABEL: combine_test7:
1223 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1224 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1227 ; SSE41-LABEL: combine_test7:
1229 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1232 ; AVX1-LABEL: combine_test7:
1234 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1237 ; AVX2-LABEL: combine_test7:
1239 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1241 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1242 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1246 define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1247 ; SSE-LABEL: combine_test8:
1249 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1252 ; AVX-LABEL: combine_test8:
1254 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1256 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1257 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1261 define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1262 ; SSE-LABEL: combine_test9:
1264 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1265 ; SSE-NEXT: movdqa %xmm1, %xmm0
1268 ; AVX-LABEL: combine_test9:
1270 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1272 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1273 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1277 define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1278 ; SSE2-LABEL: combine_test10:
1280 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1281 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1284 ; SSSE3-LABEL: combine_test10:
1286 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1287 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1290 ; SSE41-LABEL: combine_test10:
1292 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1295 ; AVX1-LABEL: combine_test10:
1297 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1300 ; AVX2-LABEL: combine_test10:
1302 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1304 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1305 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1309 define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1310 ; ALL-LABEL: combine_test11:
1313 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1314 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1318 define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1319 ; SSE2-LABEL: combine_test12:
1321 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1322 ; SSE2-NEXT: movaps %xmm1, %xmm0
1325 ; SSSE3-LABEL: combine_test12:
1327 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1328 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1331 ; SSE41-LABEL: combine_test12:
1333 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1336 ; AVX-LABEL: combine_test12:
1338 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1340 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1341 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1345 define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1346 ; SSE-LABEL: combine_test13:
1348 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1351 ; AVX-LABEL: combine_test13:
1353 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1355 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1356 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1360 define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1361 ; SSE-LABEL: combine_test14:
1363 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1366 ; AVX-LABEL: combine_test14:
1368 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1370 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1371 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1375 define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1376 ; SSE2-LABEL: combine_test15:
1378 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1379 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1382 ; SSSE3-LABEL: combine_test15:
1384 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1385 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1388 ; SSE41-LABEL: combine_test15:
1390 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1393 ; AVX-LABEL: combine_test15:
1395 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1397 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1398 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1402 define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1403 ; ALL-LABEL: combine_test16:
1406 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1407 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1411 define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1412 ; SSE2-LABEL: combine_test17:
1414 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1415 ; SSE2-NEXT: movaps %xmm1, %xmm0
1418 ; SSSE3-LABEL: combine_test17:
1420 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1421 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1424 ; SSE41-LABEL: combine_test17:
1426 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1429 ; AVX1-LABEL: combine_test17:
1431 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1434 ; AVX2-LABEL: combine_test17:
1436 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1438 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1439 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1443 define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1444 ; SSE-LABEL: combine_test18:
1446 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1449 ; AVX-LABEL: combine_test18:
1451 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1453 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1454 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1458 define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1459 ; SSE-LABEL: combine_test19:
1461 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1464 ; AVX-LABEL: combine_test19:
1466 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1468 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1469 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1473 define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1474 ; SSE2-LABEL: combine_test20:
1476 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1477 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1480 ; SSSE3-LABEL: combine_test20:
1482 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1483 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1486 ; SSE41-LABEL: combine_test20:
1488 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1491 ; AVX1-LABEL: combine_test20:
1493 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1496 ; AVX2-LABEL: combine_test20:
1498 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1500 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1501 %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1505 define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1506 ; SSE-LABEL: combine_test21:
1508 ; SSE-NEXT: movdqa %xmm0, %xmm2
1509 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1510 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1511 ; SSE-NEXT: movdqa %xmm2, (%rdi)
1514 ; AVX1-LABEL: combine_test21:
1516 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1517 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1518 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1519 ; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1520 ; AVX1-NEXT: vzeroupper
1523 ; AVX2-LABEL: combine_test21:
1525 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1526 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1527 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1528 ; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1529 ; AVX2-NEXT: vzeroupper
1531 %1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1532 %2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1533 store <4 x i32> %1, <4 x i32>* %ptr, align 16
1537 define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1538 ; SSE-LABEL: combine_test22:
1540 ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1541 ; SSE-NEXT: movhpd (%rsi), %xmm0
1544 ; AVX-LABEL: combine_test22:
1546 ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1547 ; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1549 ; Current AVX2 lowering of this is still awful, not adding a test case.
1550 %1 = load <2 x float>* %a, align 8
1551 %2 = load <2 x float>* %b, align 8
1552 %3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1556 ; Check some negative cases.
1557 ; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1559 define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1560 ; SSE-LABEL: combine_test1b:
1562 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1563 ; SSE-NEXT: movaps %xmm1, %xmm0
1566 ; AVX-LABEL: combine_test1b:
1568 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1570 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1571 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1575 define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1576 ; SSE2-LABEL: combine_test2b:
1578 ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1579 ; SSE2-NEXT: movaps %xmm1, %xmm0
1582 ; SSSE3-LABEL: combine_test2b:
1584 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1587 ; SSE41-LABEL: combine_test2b:
1589 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1592 ; AVX-LABEL: combine_test2b:
1594 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1596 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1597 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1601 define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1602 ; SSE-LABEL: combine_test3b:
1604 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1605 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1608 ; AVX-LABEL: combine_test3b:
1610 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1611 ; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1613 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1614 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1618 define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1619 ; SSE-LABEL: combine_test4b:
1621 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1622 ; SSE-NEXT: movaps %xmm1, %xmm0
1625 ; AVX-LABEL: combine_test4b:
1627 ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1629 %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1630 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1635 ; Verify that we correctly fold shuffles even when we use illegal vector types.
1637 define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1638 ; SSE2-LABEL: combine_test1c:
1640 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1641 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1642 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1643 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1644 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1645 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1646 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1649 ; SSSE3-LABEL: combine_test1c:
1651 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1652 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1653 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1654 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1655 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1656 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1657 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1660 ; SSE41-LABEL: combine_test1c:
1662 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1663 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1664 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1667 ; AVX1-LABEL: combine_test1c:
1669 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1670 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1671 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1674 ; AVX2-LABEL: combine_test1c:
1676 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1677 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1678 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1680 %A = load <4 x i8>* %a
1681 %B = load <4 x i8>* %b
1682 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1683 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1687 define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1688 ; SSE2-LABEL: combine_test2c:
1690 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1691 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1692 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1693 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1694 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1695 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1696 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1699 ; SSSE3-LABEL: combine_test2c:
1701 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1702 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1703 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1704 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1705 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1706 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1707 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1710 ; SSE41-LABEL: combine_test2c:
1712 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1713 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1714 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1717 ; AVX-LABEL: combine_test2c:
1719 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1720 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1721 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1723 %A = load <4 x i8>* %a
1724 %B = load <4 x i8>* %b
1725 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1726 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1730 define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1731 ; SSE2-LABEL: combine_test3c:
1733 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1734 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1735 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1736 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1737 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1738 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1739 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1742 ; SSSE3-LABEL: combine_test3c:
1744 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1745 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1746 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1747 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1748 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1749 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1750 ; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1753 ; SSE41-LABEL: combine_test3c:
1755 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1756 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1757 ; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1760 ; AVX-LABEL: combine_test3c:
1762 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1763 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1764 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1766 %A = load <4 x i8>* %a
1767 %B = load <4 x i8>* %b
1768 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1769 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1773 define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
1774 ; SSE2-LABEL: combine_test4c:
1776 ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1777 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1778 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1779 ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1780 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1781 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1782 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1783 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1786 ; SSSE3-LABEL: combine_test4c:
1788 ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1789 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1790 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1791 ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1792 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1793 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1794 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1795 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1798 ; SSE41-LABEL: combine_test4c:
1800 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1801 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1802 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1805 ; AVX1-LABEL: combine_test4c:
1807 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1808 ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1809 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1812 ; AVX2-LABEL: combine_test4c:
1814 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1815 ; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1816 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1818 %A = load <4 x i8>* %a
1819 %B = load <4 x i8>* %b
1820 %1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1821 %2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1826 ; The following test cases are generated from this C++ code
1828 ;__m128 blend_01(__m128 a, __m128 b)
1831 ; s = _mm_blend_ps( s, b, 1<<0 );
1832 ; s = _mm_blend_ps( s, b, 1<<1 );
1836 ;__m128 blend_02(__m128 a, __m128 b)
1839 ; s = _mm_blend_ps( s, b, 1<<0 );
1840 ; s = _mm_blend_ps( s, b, 1<<2 );
1844 ;__m128 blend_123(__m128 a, __m128 b)
1847 ; s = _mm_blend_ps( s, b, 1<<1 );
1848 ; s = _mm_blend_ps( s, b, 1<<2 );
1849 ; s = _mm_blend_ps( s, b, 1<<3 );
1853 ; Ideally, we should collapse the following shuffles into a single one.
1855 define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
1856 ; SSE2-LABEL: combine_blend_01:
1858 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1861 ; SSSE3-LABEL: combine_blend_01:
1863 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1866 ; SSE41-LABEL: combine_blend_01:
1868 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1871 ; AVX-LABEL: combine_blend_01:
1873 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1875 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
1876 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1877 ret <4 x float> %shuffle6
1880 define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
1881 ; SSE2-LABEL: combine_blend_02:
1883 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
1884 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1885 ; SSE2-NEXT: movaps %xmm1, %xmm0
1888 ; SSSE3-LABEL: combine_blend_02:
1890 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
1891 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
1892 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1895 ; SSE41-LABEL: combine_blend_02:
1897 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1900 ; AVX-LABEL: combine_blend_02:
1902 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1904 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
1905 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1906 ret <4 x float> %shuffle6
1909 define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
1910 ; SSE2-LABEL: combine_blend_123:
1912 ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1913 ; SSE2-NEXT: movaps %xmm1, %xmm0
1916 ; SSSE3-LABEL: combine_blend_123:
1918 ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1919 ; SSSE3-NEXT: movaps %xmm1, %xmm0
1922 ; SSE41-LABEL: combine_blend_123:
1924 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1927 ; AVX-LABEL: combine_blend_123:
1929 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1931 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
1932 %shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
1933 %shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1934 ret <4 x float> %shuffle12
1937 define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
1938 ; SSE-LABEL: combine_test_movhl_1:
1940 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1941 ; SSE-NEXT: movdqa %xmm1, %xmm0
1944 ; AVX-LABEL: combine_test_movhl_1:
1946 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1948 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
1949 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
1953 define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
1954 ; SSE-LABEL: combine_test_movhl_2:
1956 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1957 ; SSE-NEXT: movdqa %xmm1, %xmm0
1960 ; AVX-LABEL: combine_test_movhl_2:
1962 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1964 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
1965 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
1969 define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
1970 ; SSE-LABEL: combine_test_movhl_3:
1972 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1973 ; SSE-NEXT: movdqa %xmm1, %xmm0
1976 ; AVX-LABEL: combine_test_movhl_3:
1978 ; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1980 %1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
1981 %2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
1986 ; Verify that we fold shuffles according to rule:
1987 ; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
1989 define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
1990 ; SSE2-LABEL: combine_undef_input_test1:
1992 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1995 ; SSSE3-LABEL: combine_undef_input_test1:
1997 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2000 ; SSE41-LABEL: combine_undef_input_test1:
2002 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2005 ; AVX-LABEL: combine_undef_input_test1:
2007 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2009 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2010 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2014 define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2015 ; SSE-LABEL: combine_undef_input_test2:
2017 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2020 ; AVX-LABEL: combine_undef_input_test2:
2022 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2024 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2025 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2029 define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2030 ; SSE-LABEL: combine_undef_input_test3:
2032 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2035 ; AVX-LABEL: combine_undef_input_test3:
2037 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2039 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2040 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2044 define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2045 ; SSE-LABEL: combine_undef_input_test4:
2047 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2048 ; SSE-NEXT: movapd %xmm1, %xmm0
2051 ; AVX-LABEL: combine_undef_input_test4:
2053 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2055 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2056 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2060 define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2061 ; SSE2-LABEL: combine_undef_input_test5:
2063 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2064 ; SSE2-NEXT: movapd %xmm1, %xmm0
2067 ; SSSE3-LABEL: combine_undef_input_test5:
2069 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2070 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2073 ; SSE41-LABEL: combine_undef_input_test5:
2075 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2078 ; AVX-LABEL: combine_undef_input_test5:
2080 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2082 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2083 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2088 ; Verify that we fold shuffles according to rule:
2089 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2091 define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2092 ; ALL-LABEL: combine_undef_input_test6:
2095 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2096 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2100 define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2101 ; SSE2-LABEL: combine_undef_input_test7:
2103 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2106 ; SSSE3-LABEL: combine_undef_input_test7:
2108 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2111 ; SSE41-LABEL: combine_undef_input_test7:
2113 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2116 ; AVX-LABEL: combine_undef_input_test7:
2118 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2120 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2121 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2125 define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2126 ; SSE2-LABEL: combine_undef_input_test8:
2128 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2131 ; SSSE3-LABEL: combine_undef_input_test8:
2133 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2136 ; SSE41-LABEL: combine_undef_input_test8:
2138 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2141 ; AVX-LABEL: combine_undef_input_test8:
2143 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2145 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2146 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2150 define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2151 ; SSE-LABEL: combine_undef_input_test9:
2153 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2156 ; AVX-LABEL: combine_undef_input_test9:
2158 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2160 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2161 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2165 define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2166 ; ALL-LABEL: combine_undef_input_test10:
2169 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2170 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2174 define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2175 ; SSE2-LABEL: combine_undef_input_test11:
2177 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2180 ; SSSE3-LABEL: combine_undef_input_test11:
2182 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2185 ; SSE41-LABEL: combine_undef_input_test11:
2187 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2190 ; AVX-LABEL: combine_undef_input_test11:
2192 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2194 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2195 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2199 define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2200 ; SSE-LABEL: combine_undef_input_test12:
2202 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2205 ; AVX-LABEL: combine_undef_input_test12:
2207 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2209 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2210 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2214 define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2215 ; SSE-LABEL: combine_undef_input_test13:
2217 ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2220 ; AVX-LABEL: combine_undef_input_test13:
2222 ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2224 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2225 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2229 define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2230 ; SSE-LABEL: combine_undef_input_test14:
2232 ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2233 ; SSE-NEXT: movapd %xmm1, %xmm0
2236 ; AVX-LABEL: combine_undef_input_test14:
2238 ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2240 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2241 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2245 define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2246 ; SSE2-LABEL: combine_undef_input_test15:
2248 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2249 ; SSE2-NEXT: movapd %xmm1, %xmm0
2252 ; SSSE3-LABEL: combine_undef_input_test15:
2254 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2255 ; SSSE3-NEXT: movapd %xmm1, %xmm0
2258 ; SSE41-LABEL: combine_undef_input_test15:
2260 ; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2263 ; AVX-LABEL: combine_undef_input_test15:
2265 ; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2267 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2268 %2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2273 ; Verify that shuffles are canonicalized according to rules:
2274 ; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2276 ; This allows to trigger the following combine rule:
2277 ; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2279 ; As a result, all the shuffle pairs in each function below should be
2280 ; combined into a single legal shuffle operation.
2282 define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2283 ; ALL-LABEL: combine_undef_input_test16:
2286 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2287 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2291 define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2292 ; SSE2-LABEL: combine_undef_input_test17:
2294 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2297 ; SSSE3-LABEL: combine_undef_input_test17:
2299 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2302 ; SSE41-LABEL: combine_undef_input_test17:
2304 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2307 ; AVX-LABEL: combine_undef_input_test17:
2309 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2311 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2312 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2316 define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2317 ; SSE2-LABEL: combine_undef_input_test18:
2319 ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2322 ; SSSE3-LABEL: combine_undef_input_test18:
2324 ; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2327 ; SSE41-LABEL: combine_undef_input_test18:
2329 ; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2332 ; AVX-LABEL: combine_undef_input_test18:
2334 ; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2336 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2337 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2341 define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2342 ; SSE-LABEL: combine_undef_input_test19:
2344 ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2347 ; AVX-LABEL: combine_undef_input_test19:
2349 ; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2351 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2352 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2356 define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2357 ; ALL-LABEL: combine_undef_input_test20:
2360 %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2361 %2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2365 ; These tests are designed to test the ability to combine away unnecessary
2366 ; operations feeding into a shuffle. The AVX cases are the important ones as
2367 ; they leverage operations which cannot be done naturally on the entire vector
2368 ; and thus are decomposed into multiple smaller operations.
2370 define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2371 ; SSE-LABEL: combine_unneeded_subvector1:
2373 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2374 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2375 ; SSE-NEXT: movdqa %xmm0, %xmm1
2378 ; AVX1-LABEL: combine_unneeded_subvector1:
2380 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2381 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2382 ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2383 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2386 ; AVX2-LABEL: combine_unneeded_subvector1:
2388 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2389 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2390 ; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2392 %b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2393 %c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2397 define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2398 ; SSE-LABEL: combine_unneeded_subvector2:
2400 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2401 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2402 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2405 ; AVX1-LABEL: combine_unneeded_subvector2:
2407 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2408 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2409 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2410 ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2411 ; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2414 ; AVX2-LABEL: combine_unneeded_subvector2:
2416 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2417 ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2418 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2420 %c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2421 %d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2425 define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2426 ; SSE2-LABEL: combine_insertps1:
2428 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2429 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2430 ; SSE2-NEXT: movaps %xmm1, %xmm0
2433 ; SSSE3-LABEL: combine_insertps1:
2435 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2436 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2437 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2440 ; SSE41-LABEL: combine_insertps1:
2442 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2445 ; AVX-LABEL: combine_insertps1:
2447 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2450 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2451 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2455 define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2456 ; SSE2-LABEL: combine_insertps2:
2458 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2459 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2460 ; SSE2-NEXT: movaps %xmm1, %xmm0
2463 ; SSSE3-LABEL: combine_insertps2:
2465 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2466 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2467 ; SSSE3-NEXT: movaps %xmm1, %xmm0
2470 ; SSE41-LABEL: combine_insertps2:
2472 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2475 ; AVX-LABEL: combine_insertps2:
2477 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2480 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2481 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2485 define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2486 ; SSE2-LABEL: combine_insertps3:
2488 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2489 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2492 ; SSSE3-LABEL: combine_insertps3:
2494 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2495 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2498 ; SSE41-LABEL: combine_insertps3:
2500 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2503 ; AVX-LABEL: combine_insertps3:
2505 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2508 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2509 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2513 define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2514 ; SSE2-LABEL: combine_insertps4:
2516 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2517 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2520 ; SSSE3-LABEL: combine_insertps4:
2522 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2523 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2526 ; SSE41-LABEL: combine_insertps4:
2528 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2531 ; AVX-LABEL: combine_insertps4:
2533 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2536 %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2537 %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>