1 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X32
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X64
4 @g16 = external global i16
6 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
9 ; X32-NEXT: pinsrd $1, {{[0-9]+}}(%esp), %xmm0
12 ; X64-LABEL: pinsrd_1:
14 ; X64-NEXT: pinsrd $1, %edi, %xmm0
16 %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
20 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
21 ; X32-LABEL: pinsrb_1:
23 ; X32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
26 ; X64-LABEL: pinsrb_1:
28 ; X64-NEXT: pinsrb $1, %edi, %xmm0
30 %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
34 define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
35 ; X32-LABEL: pmovsxbd_1:
36 ; X32: ## BB#0: ## %entry
37 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
38 ; X32-NEXT: pmovsxbd (%eax), %xmm0
41 ; X64-LABEL: pmovsxbd_1:
42 ; X64: ## BB#0: ## %entry
43 ; X64-NEXT: pmovsxbd (%rdi), %xmm0
46 %0 = load i32* %p, align 4
47 %1 = insertelement <4 x i32> undef, i32 %0, i32 0
48 %2 = insertelement <4 x i32> %1, i32 0, i32 1
49 %3 = insertelement <4 x i32> %2, i32 0, i32 2
50 %4 = insertelement <4 x i32> %3, i32 0, i32 3
51 %5 = bitcast <4 x i32> %4 to <16 x i8>
52 %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
53 %7 = bitcast <4 x i32> %6 to <2 x i64>
57 define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
58 ; X32-LABEL: pmovsxwd_1:
59 ; X32: ## BB#0: ## %entry
60 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
61 ; X32-NEXT: pmovsxwd (%eax), %xmm0
64 ; X64-LABEL: pmovsxwd_1:
65 ; X64: ## BB#0: ## %entry
66 ; X64-NEXT: pmovsxwd (%rdi), %xmm0
69 %0 = load i64* %p ; <i64> [#uses=1]
70 %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
71 %1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
72 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
73 %3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
77 define <2 x i64> @pmovzxbq_1() nounwind {
78 ; X32-LABEL: pmovzxbq_1:
79 ; X32: ## BB#0: ## %entry
80 ; X32-NEXT: movl L_g16$non_lazy_ptr, %eax
81 ; X32-NEXT: pmovzxbq (%eax), %xmm0
84 ; X64-LABEL: pmovzxbq_1:
85 ; X64: ## BB#0: ## %entry
86 ; X64-NEXT: movq _g16@{{.*}}(%rip), %rax
87 ; X64-NEXT: pmovzxbq (%rax), %xmm0
90 %0 = load i16* @g16, align 2 ; <i16> [#uses=1]
91 %1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
92 %2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
93 %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
97 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
98 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
99 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
101 define i32 @extractps_1(<4 x float> %v) nounwind {
102 ; X32-LABEL: extractps_1:
104 ; X32-NEXT: extractps $3, %xmm0, %eax
107 ; X64-LABEL: extractps_1:
109 ; X64-NEXT: extractps $3, %xmm0, %eax
111 %s = extractelement <4 x float> %v, i32 3
112 %i = bitcast float %s to i32
115 define i32 @extractps_2(<4 x float> %v) nounwind {
116 ; X32-LABEL: extractps_2:
118 ; X32-NEXT: extractps $3, %xmm0, %eax
121 ; X64-LABEL: extractps_2:
123 ; X64-NEXT: extractps $3, %xmm0, %eax
125 %t = bitcast <4 x float> %v to <4 x i32>
126 %s = extractelement <4 x i32> %t, i32 3
131 ; The non-store form of extractps puts its result into a GPR.
132 ; This makes it suitable for an extract from a <4 x float> that
133 ; is bitcasted to i32, but unsuitable for much of anything else.
135 define float @ext_1(<4 x float> %v) nounwind {
138 ; X32-NEXT: pushl %eax
139 ; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
140 ; X32-NEXT: addss LCPI7_0, %xmm0
141 ; X32-NEXT: movss %xmm0, (%esp)
142 ; X32-NEXT: flds (%esp)
143 ; X32-NEXT: popl %eax
148 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
149 ; X64-NEXT: addss {{.*}}(%rip), %xmm0
151 %s = extractelement <4 x float> %v, i32 3
152 %t = fadd float %s, 1.0
155 define float @ext_2(<4 x float> %v) nounwind {
158 ; X32-NEXT: pushl %eax
159 ; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
160 ; X32-NEXT: movss %xmm0, (%esp)
161 ; X32-NEXT: flds (%esp)
162 ; X32-NEXT: popl %eax
167 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
169 %s = extractelement <4 x float> %v, i32 3
172 define i32 @ext_3(<4 x i32> %v) nounwind {
175 ; X32-NEXT: pextrd $3, %xmm0, %eax
180 ; X64-NEXT: pextrd $3, %xmm0, %eax
182 %i = extractelement <4 x i32> %v, i32 3
186 define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
187 ; X32-LABEL: insertps_1:
189 ; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
192 ; X64-LABEL: insertps_1:
194 ; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
196 %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
197 ret <4 x float> %tmp1
200 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
202 define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
203 ; X32-LABEL: insertps_2:
205 ; X32-NEXT: insertps $0, {{[0-9]+}}(%esp), %xmm0
208 ; X64-LABEL: insertps_2:
210 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
212 %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
213 ret <4 x float> %tmp1
215 define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
216 ; X32-LABEL: insertps_3:
218 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
221 ; X64-LABEL: insertps_3:
223 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
225 %tmp2 = extractelement <4 x float> %t2, i32 0
226 %tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
227 ret <4 x float> %tmp1
230 define i32 @ptestz_1(<2 x i64> %t1, <2 x i64> %t2) nounwind {
231 ; X32-LABEL: ptestz_1:
233 ; X32-NEXT: ptest %xmm1, %xmm0
235 ; X32-NEXT: movzbl %al, %eax
238 ; X64-LABEL: ptestz_1:
240 ; X64-NEXT: ptest %xmm1, %xmm0
242 ; X64-NEXT: movzbl %al, %eax
244 %tmp1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
248 define i32 @ptestz_2(<2 x i64> %t1, <2 x i64> %t2) nounwind {
249 ; X32-LABEL: ptestz_2:
251 ; X32-NEXT: ptest %xmm1, %xmm0
252 ; X32-NEXT: sbbl %eax, %eax
253 ; X32-NEXT: andl $1, %eax
256 ; X64-LABEL: ptestz_2:
258 ; X64-NEXT: ptest %xmm1, %xmm0
259 ; X64-NEXT: sbbl %eax, %eax
260 ; X64-NEXT: andl $1, %eax
262 %tmp1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
266 define i32 @ptestz_3(<2 x i64> %t1, <2 x i64> %t2) nounwind {
267 ; X32-LABEL: ptestz_3:
269 ; X32-NEXT: ptest %xmm1, %xmm0
271 ; X32-NEXT: movzbl %al, %eax
274 ; X64-LABEL: ptestz_3:
276 ; X64-NEXT: ptest %xmm1, %xmm0
278 ; X64-NEXT: movzbl %al, %eax
280 %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
285 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
286 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
287 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
289 ; This used to compile to insertps $0 + insertps $16. insertps $0 is always
291 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
292 ; X32-LABEL: buildvector:
293 ; X32: ## BB#0: ## %entry
294 ; X32-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,0,0]
295 ; X32-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,0,0,0]
296 ; X32-NEXT: addss %xmm1, %xmm0
297 ; X32-NEXT: addss %xmm2, %xmm3
298 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
301 ; X64-LABEL: buildvector:
302 ; X64: ## BB#0: ## %entry
303 ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,0,0]
304 ; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,0,0,0]
305 ; X64-NEXT: addss %xmm1, %xmm0
306 ; X64-NEXT: addss %xmm2, %xmm3
307 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
310 %tmp7 = extractelement <2 x float> %A, i32 0
311 %tmp5 = extractelement <2 x float> %A, i32 1
312 %tmp3 = extractelement <2 x float> %B, i32 0
313 %tmp1 = extractelement <2 x float> %B, i32 1
314 %add.r = fadd float %tmp7, %tmp3
315 %add.i = fadd float %tmp5, %tmp1
316 %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
317 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
318 ret <2 x float> %tmp9
321 define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
322 ; X32-LABEL: insertps_from_shufflevector_1:
323 ; X32: ## BB#0: ## %entry
324 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
325 ; X32-NEXT: insertps $48, (%eax), %xmm0
328 ; X64-LABEL: insertps_from_shufflevector_1:
329 ; X64: ## BB#0: ## %entry
330 ; X64-NEXT: insertps $48, (%rdi), %xmm0
333 %0 = load <4 x float>* %pb, align 16
334 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
335 ret <4 x float> %vecinit6
338 define <4 x float> @insertps_from_shufflevector_2(<4 x float> %a, <4 x float> %b) {
339 ; X32-LABEL: insertps_from_shufflevector_2:
340 ; X32: ## BB#0: ## %entry
341 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
344 ; X64-LABEL: insertps_from_shufflevector_2:
345 ; X64: ## BB#0: ## %entry
346 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
349 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
350 ret <4 x float> %vecinit6
353 ; For loading an i32 from memory into an xmm register we use pinsrd
354 ; instead of insertps
355 define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocapture readonly %pb) {
356 ; X32-LABEL: pinsrd_from_shufflevector_i32:
357 ; X32: ## BB#0: ## %entry
358 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
359 ; X32-NEXT: pinsrd $3, (%eax), %xmm0
362 ; X64-LABEL: pinsrd_from_shufflevector_i32:
363 ; X64: ## BB#0: ## %entry
364 ; X64-NEXT: pinsrd $3, (%rdi), %xmm0
367 %0 = load <4 x i32>* %pb, align 16
368 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
369 ret <4 x i32> %vecinit6
372 define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
373 ; X32-LABEL: insertps_from_shufflevector_i32_2:
374 ; X32: ## BB#0: ## %entry
375 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
378 ; X64-LABEL: insertps_from_shufflevector_i32_2:
379 ; X64: ## BB#0: ## %entry
380 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
383 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
384 ret <4 x i32> %vecinit6
387 define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b) {
388 ; X32-LABEL: insertps_from_load_ins_elt_undef:
390 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
391 ; X32-NEXT: insertps $16, (%eax), %xmm0
394 ; X64-LABEL: insertps_from_load_ins_elt_undef:
396 ; X64-NEXT: insertps $16, (%rdi), %xmm0
398 %1 = load float* %b, align 4
399 %2 = insertelement <4 x float> undef, float %1, i32 0
400 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
401 ret <4 x float> %result
404 ; TODO: Like on pinsrd_from_shufflevector_i32, remove this mov instr
405 define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
406 ; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
408 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
409 ; X32-NEXT: movd (%eax), %xmm1
410 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
413 ; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
415 ; X64-NEXT: movd (%rdi), %xmm1
416 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
418 %1 = load i32* %b, align 4
419 %2 = insertelement <4 x i32> undef, i32 %1, i32 0
420 %result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
421 ret <4 x i32> %result
424 ;;;;;; Shuffles optimizable with a single insertps instruction
425 define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
426 ; X32-LABEL: shuf_XYZ0:
428 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
431 ; X64-LABEL: shuf_XYZ0:
433 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
435 %vecext = extractelement <4 x float> %x, i32 0
436 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
437 %vecext1 = extractelement <4 x float> %x, i32 1
438 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
439 %vecext3 = extractelement <4 x float> %x, i32 2
440 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
441 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
442 ret <4 x float> %vecinit5
445 define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
446 ; X32-LABEL: shuf_XY00:
448 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
451 ; X64-LABEL: shuf_XY00:
453 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
455 %vecext = extractelement <4 x float> %x, i32 0
456 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
457 %vecext1 = extractelement <4 x float> %x, i32 1
458 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
459 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
460 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
461 ret <4 x float> %vecinit4
464 define <4 x float> @shuf_XYY0(<4 x float> %x, <4 x float> %a) {
465 ; X32-LABEL: shuf_XYY0:
467 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
470 ; X64-LABEL: shuf_XYY0:
472 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
474 %vecext = extractelement <4 x float> %x, i32 0
475 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
476 %vecext1 = extractelement <4 x float> %x, i32 1
477 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
478 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext1, i32 2
479 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
480 ret <4 x float> %vecinit5
483 define <4 x float> @shuf_XYW0(<4 x float> %x, <4 x float> %a) {
484 ; X32-LABEL: shuf_XYW0:
486 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
489 ; X64-LABEL: shuf_XYW0:
491 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
493 %vecext = extractelement <4 x float> %x, i32 0
494 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
495 %vecext1 = extractelement <4 x float> %x, i32 1
496 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
497 %vecext2 = extractelement <4 x float> %x, i32 3
498 %vecinit3 = insertelement <4 x float> %vecinit2, float %vecext2, i32 2
499 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
500 ret <4 x float> %vecinit4
503 define <4 x float> @shuf_W00W(<4 x float> %x, <4 x float> %a) {
504 ; X32-LABEL: shuf_W00W:
506 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
509 ; X64-LABEL: shuf_W00W:
511 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
513 %vecext = extractelement <4 x float> %x, i32 3
514 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
515 %vecinit2 = insertelement <4 x float> %vecinit, float 0.0, i32 1
516 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
517 %vecinit4 = insertelement <4 x float> %vecinit3, float %vecext, i32 3
518 ret <4 x float> %vecinit4
521 define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
522 ; X32-LABEL: shuf_X00A:
524 ; X32-NEXT: xorps %xmm2, %xmm2
525 ; X32-NEXT: movss %xmm0, %xmm2
526 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
527 ; X32-NEXT: movaps %xmm2, %xmm0
530 ; X64-LABEL: shuf_X00A:
532 ; X64-NEXT: xorps %xmm2, %xmm2
533 ; X64-NEXT: movss %xmm0, %xmm2
534 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
535 ; X64-NEXT: movaps %xmm2, %xmm0
537 %vecext = extractelement <4 x float> %x, i32 0
538 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
539 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
540 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
541 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
542 ret <4 x float> %vecinit4
545 define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
546 ; X32-LABEL: shuf_X00X:
548 ; X32-NEXT: xorps %xmm1, %xmm1
549 ; X32-NEXT: movss %xmm0, %xmm1
550 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
551 ; X32-NEXT: movaps %xmm1, %xmm0
554 ; X64-LABEL: shuf_X00X:
556 ; X64-NEXT: xorps %xmm1, %xmm1
557 ; X64-NEXT: movss %xmm0, %xmm1
558 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
559 ; X64-NEXT: movaps %xmm1, %xmm0
561 %vecext = extractelement <4 x float> %x, i32 0
562 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
563 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
564 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
565 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
566 ret <4 x float> %vecinit4
569 define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
570 ; X32-LABEL: shuf_X0YC:
572 ; X32-NEXT: xorps %xmm2, %xmm2
573 ; X32-NEXT: movss %xmm0, %xmm2
574 ; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,0]
575 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
576 ; X32-NEXT: movaps %xmm2, %xmm0
579 ; X64-LABEL: shuf_X0YC:
581 ; X64-NEXT: xorps %xmm2, %xmm2
582 ; X64-NEXT: movss %xmm0, %xmm2
583 ; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,0]
584 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
585 ; X64-NEXT: movaps %xmm2, %xmm0
587 %vecext = extractelement <4 x float> %x, i32 0
588 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
589 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
590 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
591 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
592 ret <4 x float> %vecinit5
595 define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
596 ; X32-LABEL: i32_shuf_XYZ0:
598 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
601 ; X64-LABEL: i32_shuf_XYZ0:
603 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
605 %vecext = extractelement <4 x i32> %x, i32 0
606 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
607 %vecext1 = extractelement <4 x i32> %x, i32 1
608 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
609 %vecext3 = extractelement <4 x i32> %x, i32 2
610 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
611 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
612 ret <4 x i32> %vecinit5
615 define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
616 ; X32-LABEL: i32_shuf_XY00:
618 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
621 ; X64-LABEL: i32_shuf_XY00:
623 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
625 %vecext = extractelement <4 x i32> %x, i32 0
626 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
627 %vecext1 = extractelement <4 x i32> %x, i32 1
628 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
629 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
630 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
631 ret <4 x i32> %vecinit4
634 define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
635 ; X32-LABEL: i32_shuf_XYY0:
637 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
640 ; X64-LABEL: i32_shuf_XYY0:
642 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
644 %vecext = extractelement <4 x i32> %x, i32 0
645 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
646 %vecext1 = extractelement <4 x i32> %x, i32 1
647 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
648 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext1, i32 2
649 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
650 ret <4 x i32> %vecinit5
653 define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
654 ; X32-LABEL: i32_shuf_XYW0:
656 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
659 ; X64-LABEL: i32_shuf_XYW0:
661 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
663 %vecext = extractelement <4 x i32> %x, i32 0
664 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
665 %vecext1 = extractelement <4 x i32> %x, i32 1
666 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
667 %vecext2 = extractelement <4 x i32> %x, i32 3
668 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %vecext2, i32 2
669 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
670 ret <4 x i32> %vecinit4
673 define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
674 ; X32-LABEL: i32_shuf_W00W:
676 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
679 ; X64-LABEL: i32_shuf_W00W:
681 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
683 %vecext = extractelement <4 x i32> %x, i32 3
684 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
685 %vecinit2 = insertelement <4 x i32> %vecinit, i32 0, i32 1
686 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
687 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 %vecext, i32 3
688 ret <4 x i32> %vecinit4
691 define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
692 ; X32-LABEL: i32_shuf_X00A:
694 ; X32-NEXT: xorps %xmm2, %xmm2
695 ; X32-NEXT: movss %xmm0, %xmm2
696 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
697 ; X32-NEXT: movaps %xmm2, %xmm0
700 ; X64-LABEL: i32_shuf_X00A:
702 ; X64-NEXT: xorps %xmm2, %xmm2
703 ; X64-NEXT: movss %xmm0, %xmm2
704 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
705 ; X64-NEXT: movaps %xmm2, %xmm0
707 %vecext = extractelement <4 x i32> %x, i32 0
708 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
709 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
710 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
711 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
712 ret <4 x i32> %vecinit4
715 define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
716 ; X32-LABEL: i32_shuf_X00X:
718 ; X32-NEXT: xorps %xmm1, %xmm1
719 ; X32-NEXT: movss %xmm0, %xmm1
720 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
721 ; X32-NEXT: movaps %xmm1, %xmm0
724 ; X64-LABEL: i32_shuf_X00X:
726 ; X64-NEXT: xorps %xmm1, %xmm1
727 ; X64-NEXT: movss %xmm0, %xmm1
728 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
729 ; X64-NEXT: movaps %xmm1, %xmm0
731 %vecext = extractelement <4 x i32> %x, i32 0
732 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
733 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
734 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
735 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
736 ret <4 x i32> %vecinit4
739 define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
740 ; X32-LABEL: i32_shuf_X0YC:
742 ; X32-NEXT: xorps %xmm2, %xmm2
743 ; X32-NEXT: movss %xmm0, %xmm2
744 ; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,0]
745 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
746 ; X32-NEXT: movaps %xmm2, %xmm0
749 ; X64-LABEL: i32_shuf_X0YC:
751 ; X64-NEXT: xorps %xmm2, %xmm2
752 ; X64-NEXT: movss %xmm0, %xmm2
753 ; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1,0]
754 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
755 ; X64-NEXT: movaps %xmm2, %xmm0
757 %vecext = extractelement <4 x i32> %x, i32 0
758 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
759 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
760 %vecinit3 = shufflevector <4 x i32> %vecinit1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
761 %vecinit5 = shufflevector <4 x i32> %vecinit3, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
762 ret <4 x i32> %vecinit5
765 ;; Test for a bug in the first implementation of LowerBuildVectorv4x32
766 define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
767 ; X32-LABEL: test_insertps_no_undef:
769 ; X32-NEXT: movaps %xmm0, %xmm1
770 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
771 ; X32-NEXT: maxps %xmm1, %xmm0
774 ; X64-LABEL: test_insertps_no_undef:
776 ; X64-NEXT: movaps %xmm0, %xmm1
777 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
778 ; X64-NEXT: maxps %xmm1, %xmm0
780 %vecext = extractelement <4 x float> %x, i32 0
781 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
782 %vecext1 = extractelement <4 x float> %x, i32 1
783 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
784 %vecext3 = extractelement <4 x float> %x, i32 2
785 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
786 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
787 %mask = fcmp olt <4 x float> %vecinit5, %x
788 %res = select <4 x i1> %mask, <4 x float> %x, <4 x float>%vecinit5
792 define <8 x i16> @blendvb_fallback(<8 x i1> %mask, <8 x i16> %x, <8 x i16> %y) {
793 ; X32-LABEL: blendvb_fallback:
795 ; X32-NEXT: psllw $15, %xmm0
796 ; X32-NEXT: psraw $15, %xmm0
797 ; X32-NEXT: pblendvb %xmm1, %xmm2
798 ; X32-NEXT: movdqa %xmm2, %xmm0
801 ; X64-LABEL: blendvb_fallback:
803 ; X64-NEXT: psllw $15, %xmm0
804 ; X64-NEXT: psraw $15, %xmm0
805 ; X64-NEXT: pblendvb %xmm1, %xmm2
806 ; X64-NEXT: movdqa %xmm2, %xmm0
808 %ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %y
812 ; On X32, account for the argument's move to registers
813 define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
814 ; X32-LABEL: insertps_from_vector_load:
816 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
817 ; X32-NEXT: insertps $48, (%eax), %xmm0
820 ; X64-LABEL: insertps_from_vector_load:
822 ; X64-NEXT: insertps $48, (%rdi), %xmm0
824 %1 = load <4 x float>* %pb, align 16
825 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
829 ;; Use a non-zero CountS for insertps
830 ;; Try to match a bit more of the instr, since we need the load's offset.
831 define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
832 ; X32-LABEL: insertps_from_vector_load_offset:
834 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
835 ; X32-NEXT: insertps $96, 4(%eax), %xmm0
838 ; X64-LABEL: insertps_from_vector_load_offset:
840 ; X64-NEXT: insertps $96, 4(%rdi), %xmm0
842 %1 = load <4 x float>* %pb, align 16
843 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
847 ;; Try to match a bit more of the instr, since we need the load's offset.
848 define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
849 ; X32-LABEL: insertps_from_vector_load_offset_2:
851 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
852 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
853 ; X32-NEXT: shll $4, %ecx
854 ; X32-NEXT: insertps $-64, 12(%eax,%ecx), %xmm0
857 ; X64-LABEL: insertps_from_vector_load_offset_2:
859 ; X64-NEXT: shlq $4, %rsi
860 ; X64-NEXT: insertps $-64, 12(%rdi,%rsi), %xmm0
862 %1 = getelementptr inbounds <4 x float>* %pb, i64 %index
863 %2 = load <4 x float>* %1, align 16
864 %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
868 define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
869 ; X32-LABEL: insertps_from_broadcast_loadf32:
871 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
872 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
873 ; X32-NEXT: insertps $48, (%ecx,%eax,4), %xmm0
876 ; X64-LABEL: insertps_from_broadcast_loadf32:
878 ; X64-NEXT: insertps $48, (%rdi,%rsi,4), %xmm0
880 %1 = getelementptr inbounds float* %fb, i64 %index
881 %2 = load float* %1, align 4
882 %3 = insertelement <4 x float> undef, float %2, i32 0
883 %4 = insertelement <4 x float> %3, float %2, i32 1
884 %5 = insertelement <4 x float> %4, float %2, i32 2
885 %6 = insertelement <4 x float> %5, float %2, i32 3
886 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
890 define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
891 ; X32-LABEL: insertps_from_broadcast_loadv4f32:
893 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
894 ; X32-NEXT: insertps $48, (%eax), %xmm0
897 ; X64-LABEL: insertps_from_broadcast_loadv4f32:
899 ; X64-NEXT: insertps $48, (%rdi), %xmm0
901 %1 = load <4 x float>* %b, align 4
902 %2 = extractelement <4 x float> %1, i32 0
903 %3 = insertelement <4 x float> undef, float %2, i32 0
904 %4 = insertelement <4 x float> %3, float %2, i32 1
905 %5 = insertelement <4 x float> %4, float %2, i32 2
906 %6 = insertelement <4 x float> %5, float %2, i32 3
907 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
911 ;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
912 define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
913 ; X32-LABEL: insertps_from_broadcast_multiple_use:
915 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
916 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
917 ; X32-NEXT: movss (%ecx,%eax,4), %xmm4
918 ; X32-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
919 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
920 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
921 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
922 ; X32-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
923 ; X32-NEXT: addps %xmm1, %xmm0
924 ; X32-NEXT: addps %xmm2, %xmm3
925 ; X32-NEXT: addps %xmm3, %xmm0
928 ; X64-LABEL: insertps_from_broadcast_multiple_use:
930 ; X64-NEXT: movss (%rdi,%rsi,4), %xmm4
931 ; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
932 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
933 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
934 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
935 ; X64-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
936 ; X64-NEXT: addps %xmm1, %xmm0
937 ; X64-NEXT: addps %xmm2, %xmm3
938 ; X64-NEXT: addps %xmm3, %xmm0
940 %1 = getelementptr inbounds float* %fb, i64 %index
941 %2 = load float* %1, align 4
942 %3 = insertelement <4 x float> undef, float %2, i32 0
943 %4 = insertelement <4 x float> %3, float %2, i32 1
944 %5 = insertelement <4 x float> %4, float %2, i32 2
945 %6 = insertelement <4 x float> %5, float %2, i32 3
946 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
947 %8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
948 %9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
949 %10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
950 %11 = fadd <4 x float> %7, %8
951 %12 = fadd <4 x float> %9, %10
952 %13 = fadd <4 x float> %11, %12
956 define <4 x float> @insertps_with_undefs(<4 x float> %a, float* %b) {
957 ; X32-LABEL: insertps_with_undefs:
959 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
960 ; X32-NEXT: movss (%eax), %xmm1
961 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0],xmm1[3]
962 ; X32-NEXT: movaps %xmm1, %xmm0
965 ; X64-LABEL: insertps_with_undefs:
967 ; X64-NEXT: movss (%rdi), %xmm1
968 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0],xmm1[3]
969 ; X64-NEXT: movaps %xmm1, %xmm0
971 %1 = load float* %b, align 4
972 %2 = insertelement <4 x float> undef, float %1, i32 0
973 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 4, i32 undef, i32 0, i32 7>
974 ret <4 x float> %result
977 ; Test for a bug in X86ISelLowering.cpp:getINSERTPS where we were using
978 ; the destination index to change the load, instead of the source index.
979 define <4 x float> @pr20087(<4 x float> %a, <4 x float> *%ptr) {
980 ; X32-LABEL: pr20087:
982 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
983 ; X32-NEXT: insertps $48, 8(%eax), %xmm0
986 ; X64-LABEL: pr20087:
988 ; X64-NEXT: insertps $48, 8(%rdi), %xmm0
990 %load = load <4 x float> *%ptr
991 %ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
995 ; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
996 define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
997 ; X32-LABEL: insertps_pr20411:
999 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1000 ; X32-NEXT: movaps {{.*#+}} xmm0 = [4,5,6,7]
1001 ; X32-NEXT: pshufd {{.*#+}} xmm1 = mem[3,0,0,0]
1002 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[3],xmm1[2,3]
1003 ; X32-NEXT: movups %xmm1, (%eax)
1006 ; X64-LABEL: insertps_pr20411:
1008 ; X64-NEXT: movaps {{.*#+}} xmm0 = [4,5,6,7]
1009 ; X64-NEXT: pshufd {{.*#+}} xmm1 = mem[3,0,0,0]
1010 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[3],xmm1[2,3]
1011 ; X64-NEXT: movups %xmm1, (%rdi)
1013 %gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1014 %shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; 4 5 6 7
1015 %shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
1016 %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
1017 %ptrcast = bitcast i32* %RET to <4 x i32>*
1018 store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4