1 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X32
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X64
4 @g16 = external global i16
6 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
9 ; X32-NEXT: pinsrd $1, {{[0-9]+}}(%esp), %xmm0
12 ; X64-LABEL: pinsrd_1:
14 ; X64-NEXT: pinsrd $1, %edi, %xmm0
16 %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
20 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
21 ; X32-LABEL: pinsrb_1:
23 ; X32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
26 ; X64-LABEL: pinsrb_1:
28 ; X64-NEXT: pinsrb $1, %edi, %xmm0
30 %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
34 define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
35 ; X32-LABEL: pmovsxbd_1:
36 ; X32: ## BB#0: ## %entry
37 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
38 ; X32-NEXT: pmovsxbd (%eax), %xmm0
41 ; X64-LABEL: pmovsxbd_1:
42 ; X64: ## BB#0: ## %entry
43 ; X64-NEXT: pmovsxbd (%rdi), %xmm0
46 %0 = load i32, i32* %p, align 4
47 %1 = insertelement <4 x i32> undef, i32 %0, i32 0
48 %2 = insertelement <4 x i32> %1, i32 0, i32 1
49 %3 = insertelement <4 x i32> %2, i32 0, i32 2
50 %4 = insertelement <4 x i32> %3, i32 0, i32 3
51 %5 = bitcast <4 x i32> %4 to <16 x i8>
52 %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
53 %7 = bitcast <4 x i32> %6 to <2 x i64>
57 define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
58 ; X32-LABEL: pmovsxwd_1:
59 ; X32: ## BB#0: ## %entry
60 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
61 ; X32-NEXT: pmovsxwd (%eax), %xmm0
64 ; X64-LABEL: pmovsxwd_1:
65 ; X64: ## BB#0: ## %entry
66 ; X64-NEXT: pmovsxwd (%rdi), %xmm0
69 %0 = load i64, i64* %p ; <i64> [#uses=1]
70 %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
71 %1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
72 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
73 %3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
77 define <2 x i64> @pmovzxbq_1() nounwind {
78 ; X32-LABEL: pmovzxbq_1:
79 ; X32: ## BB#0: ## %entry
80 ; X32-NEXT: movl L_g16$non_lazy_ptr, %eax
81 ; X32-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
84 ; X64-LABEL: pmovzxbq_1:
85 ; X64: ## BB#0: ## %entry
86 ; X64-NEXT: movq _g16@{{.*}}(%rip), %rax
87 ; X64-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
90 %0 = load i16, i16* @g16, align 2 ; <i16> [#uses=1]
91 %1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
92 %2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
93 %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
97 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
98 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
99 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
101 define i32 @extractps_1(<4 x float> %v) nounwind {
102 ; X32-LABEL: extractps_1:
104 ; X32-NEXT: extractps $3, %xmm0, %eax
107 ; X64-LABEL: extractps_1:
109 ; X64-NEXT: extractps $3, %xmm0, %eax
111 %s = extractelement <4 x float> %v, i32 3
112 %i = bitcast float %s to i32
115 define i32 @extractps_2(<4 x float> %v) nounwind {
116 ; X32-LABEL: extractps_2:
118 ; X32-NEXT: extractps $3, %xmm0, %eax
121 ; X64-LABEL: extractps_2:
123 ; X64-NEXT: extractps $3, %xmm0, %eax
125 %t = bitcast <4 x float> %v to <4 x i32>
126 %s = extractelement <4 x i32> %t, i32 3
131 ; The non-store form of extractps puts its result into a GPR.
132 ; This makes it suitable for an extract from a <4 x float> that
133 ; is bitcasted to i32, but unsuitable for much of anything else.
135 define float @ext_1(<4 x float> %v) nounwind {
138 ; X32-NEXT: pushl %eax
139 ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
140 ; X32-NEXT: addss LCPI7_0, %xmm0
141 ; X32-NEXT: movss %xmm0, (%esp)
142 ; X32-NEXT: flds (%esp)
143 ; X32-NEXT: popl %eax
148 ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
149 ; X64-NEXT: addss {{.*}}(%rip), %xmm0
151 %s = extractelement <4 x float> %v, i32 3
152 %t = fadd float %s, 1.0
155 define float @ext_2(<4 x float> %v) nounwind {
158 ; X32-NEXT: pushl %eax
159 ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
160 ; X32-NEXT: movss %xmm0, (%esp)
161 ; X32-NEXT: flds (%esp)
162 ; X32-NEXT: popl %eax
167 ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
169 %s = extractelement <4 x float> %v, i32 3
172 define i32 @ext_3(<4 x i32> %v) nounwind {
175 ; X32-NEXT: pextrd $3, %xmm0, %eax
180 ; X64-NEXT: pextrd $3, %xmm0, %eax
182 %i = extractelement <4 x i32> %v, i32 3
186 define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
187 ; X32-LABEL: insertps_1:
189 ; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
192 ; X64-LABEL: insertps_1:
194 ; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
196 %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
197 ret <4 x float> %tmp1
200 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
202 define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
203 ; X32-LABEL: insertps_2:
205 ; X32-NEXT: insertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
208 ; X64-LABEL: insertps_2:
210 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
212 %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
213 ret <4 x float> %tmp1
215 define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
216 ; X32-LABEL: insertps_3:
218 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
221 ; X64-LABEL: insertps_3:
223 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
225 %tmp2 = extractelement <4 x float> %t2, i32 0
226 %tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
227 ret <4 x float> %tmp1
230 define i32 @ptestz_1(<2 x i64> %t1, <2 x i64> %t2) nounwind {
231 ; X32-LABEL: ptestz_1:
233 ; X32-NEXT: ptest %xmm1, %xmm0
235 ; X32-NEXT: movzbl %al, %eax
238 ; X64-LABEL: ptestz_1:
240 ; X64-NEXT: ptest %xmm1, %xmm0
242 ; X64-NEXT: movzbl %al, %eax
244 %tmp1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
248 define i32 @ptestz_2(<2 x i64> %t1, <2 x i64> %t2) nounwind {
249 ; X32-LABEL: ptestz_2:
251 ; X32-NEXT: ptest %xmm1, %xmm0
252 ; X32-NEXT: sbbl %eax, %eax
253 ; X32-NEXT: andl $1, %eax
256 ; X64-LABEL: ptestz_2:
258 ; X64-NEXT: ptest %xmm1, %xmm0
259 ; X64-NEXT: sbbl %eax, %eax
260 ; X64-NEXT: andl $1, %eax
262 %tmp1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
266 define i32 @ptestz_3(<2 x i64> %t1, <2 x i64> %t2) nounwind {
267 ; X32-LABEL: ptestz_3:
269 ; X32-NEXT: ptest %xmm1, %xmm0
271 ; X32-NEXT: movzbl %al, %eax
274 ; X64-LABEL: ptestz_3:
276 ; X64-NEXT: ptest %xmm1, %xmm0
278 ; X64-NEXT: movzbl %al, %eax
280 %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
285 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
286 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
287 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
289 ; This used to compile to insertps $0 + insertps $16. insertps $0 is always
291 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
292 ; X32-LABEL: buildvector:
293 ; X32: ## BB#0: ## %entry
294 ; X32-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
295 ; X32-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
296 ; X32-NEXT: addss %xmm1, %xmm0
297 ; X32-NEXT: addss %xmm2, %xmm3
298 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
301 ; X64-LABEL: buildvector:
302 ; X64: ## BB#0: ## %entry
303 ; X64-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
304 ; X64-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
305 ; X64-NEXT: addss %xmm1, %xmm0
306 ; X64-NEXT: addss %xmm2, %xmm3
307 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3]
310 %tmp7 = extractelement <2 x float> %A, i32 0
311 %tmp5 = extractelement <2 x float> %A, i32 1
312 %tmp3 = extractelement <2 x float> %B, i32 0
313 %tmp1 = extractelement <2 x float> %B, i32 1
314 %add.r = fadd float %tmp7, %tmp3
315 %add.i = fadd float %tmp5, %tmp1
316 %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
317 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
318 ret <2 x float> %tmp9
321 define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
322 ; X32-LABEL: insertps_from_shufflevector_1:
323 ; X32: ## BB#0: ## %entry
324 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
325 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
328 ; X64-LABEL: insertps_from_shufflevector_1:
329 ; X64: ## BB#0: ## %entry
330 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
333 %0 = load <4 x float>, <4 x float>* %pb, align 16
334 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
335 ret <4 x float> %vecinit6
338 define <4 x float> @insertps_from_shufflevector_2(<4 x float> %a, <4 x float> %b) {
339 ; X32-LABEL: insertps_from_shufflevector_2:
340 ; X32: ## BB#0: ## %entry
341 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
344 ; X64-LABEL: insertps_from_shufflevector_2:
345 ; X64: ## BB#0: ## %entry
346 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
349 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
350 ret <4 x float> %vecinit6
353 ; For loading an i32 from memory into an xmm register we use pinsrd
354 ; instead of insertps
355 define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocapture readonly %pb) {
356 ; X32-LABEL: pinsrd_from_shufflevector_i32:
357 ; X32: ## BB#0: ## %entry
358 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
359 ; X32-NEXT: pshufd {{.*#+}} xmm1 = mem[0,1,2,0]
360 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
363 ; X64-LABEL: pinsrd_from_shufflevector_i32:
364 ; X64: ## BB#0: ## %entry
365 ; X64-NEXT: pshufd {{.*#+}} xmm1 = mem[0,1,2,0]
366 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
369 %0 = load <4 x i32>, <4 x i32>* %pb, align 16
370 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
371 ret <4 x i32> %vecinit6
374 define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
375 ; X32-LABEL: insertps_from_shufflevector_i32_2:
376 ; X32: ## BB#0: ## %entry
377 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
378 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
381 ; X64-LABEL: insertps_from_shufflevector_i32_2:
382 ; X64: ## BB#0: ## %entry
383 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
384 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
387 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
388 ret <4 x i32> %vecinit6
391 define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b) {
392 ; X32-LABEL: insertps_from_load_ins_elt_undef:
394 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
395 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
398 ; X64-LABEL: insertps_from_load_ins_elt_undef:
400 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
402 %1 = load float, float* %b, align 4
403 %2 = insertelement <4 x float> undef, float %1, i32 0
404 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
405 ret <4 x float> %result
408 ; TODO: Like on pinsrd_from_shufflevector_i32, remove this mov instr
409 define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
410 ; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
412 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
413 ; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
414 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
415 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
418 ; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
420 ; X64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
421 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
422 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
424 %1 = load i32, i32* %b, align 4
425 %2 = insertelement <4 x i32> undef, i32 %1, i32 0
426 %result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
427 ret <4 x i32> %result
430 ;;;;;; Shuffles optimizable with a single insertps or blend instruction
431 define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
432 ; X32-LABEL: shuf_XYZ0:
434 ; X32-NEXT: xorps %xmm1, %xmm1
435 ; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
438 ; X64-LABEL: shuf_XYZ0:
440 ; X64-NEXT: xorps %xmm1, %xmm1
441 ; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
443 %vecext = extractelement <4 x float> %x, i32 0
444 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
445 %vecext1 = extractelement <4 x float> %x, i32 1
446 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
447 %vecext3 = extractelement <4 x float> %x, i32 2
448 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
449 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
450 ret <4 x float> %vecinit5
453 define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
454 ; X32-LABEL: shuf_XY00:
456 ; X32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
459 ; X64-LABEL: shuf_XY00:
461 ; X64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
463 %vecext = extractelement <4 x float> %x, i32 0
464 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
465 %vecext1 = extractelement <4 x float> %x, i32 1
466 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
467 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
468 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
469 ret <4 x float> %vecinit4
472 define <4 x float> @shuf_XYY0(<4 x float> %x, <4 x float> %a) {
473 ; X32-LABEL: shuf_XYY0:
475 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
478 ; X64-LABEL: shuf_XYY0:
480 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
482 %vecext = extractelement <4 x float> %x, i32 0
483 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
484 %vecext1 = extractelement <4 x float> %x, i32 1
485 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
486 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext1, i32 2
487 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
488 ret <4 x float> %vecinit5
491 define <4 x float> @shuf_XYW0(<4 x float> %x, <4 x float> %a) {
492 ; X32-LABEL: shuf_XYW0:
494 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
497 ; X64-LABEL: shuf_XYW0:
499 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
501 %vecext = extractelement <4 x float> %x, i32 0
502 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
503 %vecext1 = extractelement <4 x float> %x, i32 1
504 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
505 %vecext2 = extractelement <4 x float> %x, i32 3
506 %vecinit3 = insertelement <4 x float> %vecinit2, float %vecext2, i32 2
507 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
508 ret <4 x float> %vecinit4
511 define <4 x float> @shuf_W00W(<4 x float> %x, <4 x float> %a) {
512 ; X32-LABEL: shuf_W00W:
514 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
517 ; X64-LABEL: shuf_W00W:
519 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
521 %vecext = extractelement <4 x float> %x, i32 3
522 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
523 %vecinit2 = insertelement <4 x float> %vecinit, float 0.0, i32 1
524 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
525 %vecinit4 = insertelement <4 x float> %vecinit3, float %vecext, i32 3
526 ret <4 x float> %vecinit4
529 define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
530 ; X32-LABEL: shuf_X00A:
532 ; X32-NEXT: xorps %xmm2, %xmm2
533 ; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
534 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
537 ; X64-LABEL: shuf_X00A:
539 ; X64-NEXT: xorps %xmm2, %xmm2
540 ; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
541 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
543 %vecext = extractelement <4 x float> %x, i32 0
544 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
545 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
546 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
547 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
548 ret <4 x float> %vecinit4
551 define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
552 ; X32-LABEL: shuf_X00X:
554 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]
557 ; X64-LABEL: shuf_X00X:
559 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]
561 %vecext = extractelement <4 x float> %x, i32 0
562 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
563 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
564 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
565 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
566 ret <4 x float> %vecinit4
569 define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
570 ; X32-LABEL: shuf_X0YC:
572 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
573 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
576 ; X64-LABEL: shuf_X0YC:
578 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
579 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
581 %vecext = extractelement <4 x float> %x, i32 0
582 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
583 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
584 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
585 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
586 ret <4 x float> %vecinit5
589 define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
590 ; X32-LABEL: i32_shuf_XYZ0:
592 ; X32-NEXT: pxor %xmm1, %xmm1
593 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
596 ; X64-LABEL: i32_shuf_XYZ0:
598 ; X64-NEXT: pxor %xmm1, %xmm1
599 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
601 %vecext = extractelement <4 x i32> %x, i32 0
602 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
603 %vecext1 = extractelement <4 x i32> %x, i32 1
604 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
605 %vecext3 = extractelement <4 x i32> %x, i32 2
606 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
607 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
608 ret <4 x i32> %vecinit5
611 define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
612 ; X32-LABEL: i32_shuf_XY00:
614 ; X32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
617 ; X64-LABEL: i32_shuf_XY00:
619 ; X64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
621 %vecext = extractelement <4 x i32> %x, i32 0
622 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
623 %vecext1 = extractelement <4 x i32> %x, i32 1
624 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
625 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
626 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
627 ret <4 x i32> %vecinit4
630 define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
631 ; X32-LABEL: i32_shuf_XYY0:
633 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
634 ; X32-NEXT: pxor %xmm0, %xmm0
635 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
638 ; X64-LABEL: i32_shuf_XYY0:
640 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
641 ; X64-NEXT: pxor %xmm0, %xmm0
642 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
644 %vecext = extractelement <4 x i32> %x, i32 0
645 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
646 %vecext1 = extractelement <4 x i32> %x, i32 1
647 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
648 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext1, i32 2
649 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
650 ret <4 x i32> %vecinit5
653 define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
654 ; X32-LABEL: i32_shuf_XYW0:
656 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,3,3]
657 ; X32-NEXT: pxor %xmm0, %xmm0
658 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
661 ; X64-LABEL: i32_shuf_XYW0:
663 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,3,3]
664 ; X64-NEXT: pxor %xmm0, %xmm0
665 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
667 %vecext = extractelement <4 x i32> %x, i32 0
668 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
669 %vecext1 = extractelement <4 x i32> %x, i32 1
670 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
671 %vecext2 = extractelement <4 x i32> %x, i32 3
672 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %vecext2, i32 2
673 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
674 ret <4 x i32> %vecinit4
677 define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
678 ; X32-LABEL: i32_shuf_W00W:
680 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
681 ; X32-NEXT: pxor %xmm0, %xmm0
682 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
685 ; X64-LABEL: i32_shuf_W00W:
687 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
688 ; X64-NEXT: pxor %xmm0, %xmm0
689 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
691 %vecext = extractelement <4 x i32> %x, i32 3
692 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
693 %vecinit2 = insertelement <4 x i32> %vecinit, i32 0, i32 1
694 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
695 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 %vecext, i32 3
696 ret <4 x i32> %vecinit4
699 define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
700 ; X32-LABEL: i32_shuf_X00A:
702 ; X32-NEXT: pxor %xmm2, %xmm2
703 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
704 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
705 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
708 ; X64-LABEL: i32_shuf_X00A:
710 ; X64-NEXT: pxor %xmm2, %xmm2
711 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
712 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
713 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
715 %vecext = extractelement <4 x i32> %x, i32 0
716 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
717 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
718 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
719 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
720 ret <4 x i32> %vecinit4
723 define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
724 ; X32-LABEL: i32_shuf_X00X:
726 ; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,2,0]
727 ; X32-NEXT: pxor %xmm0, %xmm0
728 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
731 ; X64-LABEL: i32_shuf_X00X:
733 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,2,0]
734 ; X64-NEXT: pxor %xmm0, %xmm0
735 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
737 %vecext = extractelement <4 x i32> %x, i32 0
738 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
739 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
740 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
741 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
742 ret <4 x i32> %vecinit4
745 define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
746 ; X32-LABEL: i32_shuf_X0YC:
748 ; X32-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
749 ; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
750 ; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
753 ; X64-LABEL: i32_shuf_X0YC:
755 ; X64-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
756 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
757 ; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
759 %vecext = extractelement <4 x i32> %x, i32 0
760 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
761 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
762 %vecinit3 = shufflevector <4 x i32> %vecinit1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
763 %vecinit5 = shufflevector <4 x i32> %vecinit3, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
764 ret <4 x i32> %vecinit5
767 ;; Test for a bug in the first implementation of LowerBuildVectorv4x32
768 define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
769 ; X32-LABEL: test_insertps_no_undef:
771 ; X32-NEXT: xorps %xmm1, %xmm1
772 ; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
773 ; X32-NEXT: maxps %xmm1, %xmm0
776 ; X64-LABEL: test_insertps_no_undef:
778 ; X64-NEXT: xorps %xmm1, %xmm1
779 ; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
780 ; X64-NEXT: maxps %xmm1, %xmm0
782 %vecext = extractelement <4 x float> %x, i32 0
783 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
784 %vecext1 = extractelement <4 x float> %x, i32 1
785 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
786 %vecext3 = extractelement <4 x float> %x, i32 2
787 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
788 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
789 %mask = fcmp olt <4 x float> %vecinit5, %x
790 %res = select <4 x i1> %mask, <4 x float> %x, <4 x float>%vecinit5
794 define <8 x i16> @blendvb_fallback(<8 x i1> %mask, <8 x i16> %x, <8 x i16> %y) {
795 ; X32-LABEL: blendvb_fallback:
797 ; X32-NEXT: psllw $15, %xmm0
798 ; X32-NEXT: psraw $15, %xmm0
799 ; X32-NEXT: pblendvb %xmm1, %xmm2
800 ; X32-NEXT: movdqa %xmm2, %xmm0
803 ; X64-LABEL: blendvb_fallback:
805 ; X64-NEXT: psllw $15, %xmm0
806 ; X64-NEXT: psraw $15, %xmm0
807 ; X64-NEXT: pblendvb %xmm1, %xmm2
808 ; X64-NEXT: movdqa %xmm2, %xmm0
810 %ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %y
814 ; On X32, account for the argument's move to registers
815 define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
816 ; X32-LABEL: insertps_from_vector_load:
818 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
819 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
822 ; X64-LABEL: insertps_from_vector_load:
824 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
826 %1 = load <4 x float>, <4 x float>* %pb, align 16
827 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
831 ;; Use a non-zero CountS for insertps
832 ;; Try to match a bit more of the instr, since we need the load's offset.
833 define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
834 ; X32-LABEL: insertps_from_vector_load_offset:
836 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
837 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[1],xmm0[3]
840 ; X64-LABEL: insertps_from_vector_load_offset:
842 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[1],xmm0[3]
844 %1 = load <4 x float>, <4 x float>* %pb, align 16
845 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
849 ;; Try to match a bit more of the instr, since we need the load's offset.
850 define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
851 ; X32-LABEL: insertps_from_vector_load_offset_2:
853 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
854 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
855 ; X32-NEXT: shll $4, %ecx
856 ; X32-NEXT: insertps {{.*#+}} xmm0 = mem[3],xmm0[1,2,3]
859 ; X64-LABEL: insertps_from_vector_load_offset_2:
861 ; X64-NEXT: shlq $4, %rsi
862 ; X64-NEXT: insertps {{.*#+}} xmm0 = mem[3],xmm0[1,2,3]
864 %1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
865 %2 = load <4 x float>, <4 x float>* %1, align 16
866 %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
870 define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
871 ; X32-LABEL: insertps_from_broadcast_loadf32:
873 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
874 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
875 ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
876 ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
877 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
880 ; X64-LABEL: insertps_from_broadcast_loadf32:
882 ; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
883 ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
884 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
886 %1 = getelementptr inbounds float, float* %fb, i64 %index
887 %2 = load float, float* %1, align 4
888 %3 = insertelement <4 x float> undef, float %2, i32 0
889 %4 = insertelement <4 x float> %3, float %2, i32 1
890 %5 = insertelement <4 x float> %4, float %2, i32 2
891 %6 = insertelement <4 x float> %5, float %2, i32 3
892 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
896 define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
897 ; X32-LABEL: insertps_from_broadcast_loadv4f32:
899 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
900 ; X32-NEXT: movups (%eax), %xmm1
901 ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
902 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
905 ; X64-LABEL: insertps_from_broadcast_loadv4f32:
907 ; X64-NEXT: movups (%rdi), %xmm1
908 ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
909 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
911 %1 = load <4 x float>, <4 x float>* %b, align 4
912 %2 = extractelement <4 x float> %1, i32 0
913 %3 = insertelement <4 x float> undef, float %2, i32 0
914 %4 = insertelement <4 x float> %3, float %2, i32 1
915 %5 = insertelement <4 x float> %4, float %2, i32 2
916 %6 = insertelement <4 x float> %5, float %2, i32 3
917 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
921 ;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
922 define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
923 ; X32-LABEL: insertps_from_broadcast_multiple_use:
925 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
926 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
927 ; X32-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
928 ; X32-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
929 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
930 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
931 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
932 ; X32-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
933 ; X32-NEXT: addps %xmm1, %xmm0
934 ; X32-NEXT: addps %xmm2, %xmm3
935 ; X32-NEXT: addps %xmm3, %xmm0
938 ; X64-LABEL: insertps_from_broadcast_multiple_use:
940 ; X64-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
941 ; X64-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
942 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
943 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
944 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
945 ; X64-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
946 ; X64-NEXT: addps %xmm1, %xmm0
947 ; X64-NEXT: addps %xmm2, %xmm3
948 ; X64-NEXT: addps %xmm3, %xmm0
950 %1 = getelementptr inbounds float, float* %fb, i64 %index
951 %2 = load float, float* %1, align 4
952 %3 = insertelement <4 x float> undef, float %2, i32 0
953 %4 = insertelement <4 x float> %3, float %2, i32 1
954 %5 = insertelement <4 x float> %4, float %2, i32 2
955 %6 = insertelement <4 x float> %5, float %2, i32 3
956 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
957 %8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
958 %9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
959 %10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
960 %11 = fadd <4 x float> %7, %8
961 %12 = fadd <4 x float> %9, %10
962 %13 = fadd <4 x float> %11, %12
966 define <4 x float> @insertps_with_undefs(<4 x float> %a, float* %b) {
967 ; X32-LABEL: insertps_with_undefs:
969 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
970 ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
971 ; X32-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
972 ; X32-NEXT: movapd %xmm1, %xmm0
975 ; X64-LABEL: insertps_with_undefs:
977 ; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
978 ; X64-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
979 ; X64-NEXT: movapd %xmm1, %xmm0
981 %1 = load float, float* %b, align 4
982 %2 = insertelement <4 x float> undef, float %1, i32 0
983 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 4, i32 undef, i32 0, i32 7>
984 ret <4 x float> %result
987 ; Test for a bug in X86ISelLowering.cpp:getINSERTPS where we were using
988 ; the destination index to change the load, instead of the source index.
989 define <4 x float> @pr20087(<4 x float> %a, <4 x float> *%ptr) {
990 ; X32-LABEL: pr20087:
992 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
993 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],mem[2]
996 ; X64-LABEL: pr20087:
998 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],mem[2]
1000 %load = load <4 x float> , <4 x float> *%ptr
1001 %ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
1002 ret <4 x float> %ret
1005 ; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
1006 define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
1007 ; X32-LABEL: insertps_pr20411:
1009 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1010 ; X32-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,0,1]
1011 ; X32-NEXT: pshufd {{.*#+}} xmm1 = mem[3,1,2,3]
1012 ; X32-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1013 ; X32-NEXT: movdqu %xmm1, (%eax)
1016 ; X64-LABEL: insertps_pr20411:
1018 ; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,0,1]
1019 ; X64-NEXT: pshufd {{.*#+}} xmm1 = mem[3,1,2,3]
1020 ; X64-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1021 ; X64-NEXT: movdqu %xmm1, (%rdi)
1023 %gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1024 %shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; 4 5 6 7
1025 %shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
1026 %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
1027 %ptrcast = bitcast i32* %RET to <4 x i32>*
1028 store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4
1032 define <4 x float> @insertps_4(<4 x float> %A, <4 x float> %B) {
1033 ; X32-LABEL: insertps_4:
1034 ; X32: ## BB#0: ## %entry
1035 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
1038 ; X64-LABEL: insertps_4:
1039 ; X64: ## BB#0: ## %entry
1040 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
1043 %vecext = extractelement <4 x float> %A, i32 0
1044 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
1045 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
1046 %vecext2 = extractelement <4 x float> %B, i32 2
1047 %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
1048 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
1049 ret <4 x float> %vecinit4
1052 define <4 x float> @insertps_5(<4 x float> %A, <4 x float> %B) {
1053 ; X32-LABEL: insertps_5:
1054 ; X32: ## BB#0: ## %entry
1055 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
1058 ; X64-LABEL: insertps_5:
1059 ; X64: ## BB#0: ## %entry
1060 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
1063 %vecext = extractelement <4 x float> %A, i32 0
1064 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
1065 %vecext1 = extractelement <4 x float> %B, i32 1
1066 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
1067 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
1068 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
1069 ret <4 x float> %vecinit4
1072 define <4 x float> @insertps_6(<4 x float> %A, <4 x float> %B) {
1073 ; X32-LABEL: insertps_6:
1074 ; X32: ## BB#0: ## %entry
1075 ; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
1078 ; X64-LABEL: insertps_6:
1079 ; X64: ## BB#0: ## %entry
1080 ; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
1083 %vecext = extractelement <4 x float> %A, i32 1
1084 %vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
1085 %vecext1 = extractelement <4 x float> %B, i32 2
1086 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
1087 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
1088 ret <4 x float> %vecinit3
1091 define <4 x float> @insertps_7(<4 x float> %A, <4 x float> %B) {
1092 ; X32-LABEL: insertps_7:
1093 ; X32: ## BB#0: ## %entry
1094 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
1097 ; X64-LABEL: insertps_7:
1098 ; X64: ## BB#0: ## %entry
1099 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
1102 %vecext = extractelement <4 x float> %A, i32 0
1103 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
1104 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
1105 %vecext2 = extractelement <4 x float> %B, i32 1
1106 %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
1107 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
1108 ret <4 x float> %vecinit4
1111 define <4 x float> @insertps_8(<4 x float> %A, <4 x float> %B) {
1112 ; X32-LABEL: insertps_8:
1113 ; X32: ## BB#0: ## %entry
1114 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
1117 ; X64-LABEL: insertps_8:
1118 ; X64: ## BB#0: ## %entry
1119 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
1122 %vecext = extractelement <4 x float> %A, i32 0
1123 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
1124 %vecext1 = extractelement <4 x float> %B, i32 0
1125 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
1126 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
1127 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
1128 ret <4 x float> %vecinit4
1131 define <4 x float> @insertps_9(<4 x float> %A, <4 x float> %B) {
1132 ; X32-LABEL: insertps_9:
1133 ; X32: ## BB#0: ## %entry
1134 ; X32-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
1135 ; X32-NEXT: movaps %xmm1, %xmm0
1138 ; X64-LABEL: insertps_9:
1139 ; X64: ## BB#0: ## %entry
1140 ; X64-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
1141 ; X64-NEXT: movaps %xmm1, %xmm0
1144 %vecext = extractelement <4 x float> %A, i32 0
1145 %vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
1146 %vecext1 = extractelement <4 x float> %B, i32 2
1147 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
1148 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
1149 ret <4 x float> %vecinit3
1152 define <4 x float> @insertps_10(<4 x float> %A)
1153 ; X32-LABEL: insertps_10:
1155 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
1158 ; X64-LABEL: insertps_10:
1160 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
1163 %vecext = extractelement <4 x float> %A, i32 0
1164 %vecbuild1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %vecext, i32 0
1165 %vecbuild2 = insertelement <4 x float> %vecbuild1, float %vecext, i32 2
1166 ret <4 x float> %vecbuild2
1169 define <4 x float> @build_vector_to_shuffle_1(<4 x float> %A) {
1170 ; X32-LABEL: build_vector_to_shuffle_1:
1171 ; X32: ## BB#0: ## %entry
1172 ; X32-NEXT: xorps %xmm1, %xmm1
1173 ; X32-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1176 ; X64-LABEL: build_vector_to_shuffle_1:
1177 ; X64: ## BB#0: ## %entry
1178 ; X64-NEXT: xorps %xmm1, %xmm1
1179 ; X64-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
1182 %vecext = extractelement <4 x float> %A, i32 1
1183 %vecinit = insertelement <4 x float> zeroinitializer, float %vecext, i32 1
1184 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 2
1185 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1186 ret <4 x float> %vecinit3
1189 define <4 x float> @build_vector_to_shuffle_2(<4 x float> %A) {
1190 ; X32-LABEL: build_vector_to_shuffle_2:
1191 ; X32: ## BB#0: ## %entry
1192 ; X32-NEXT: xorps %xmm1, %xmm1
1193 ; X32-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1196 ; X64-LABEL: build_vector_to_shuffle_2:
1197 ; X64: ## BB#0: ## %entry
1198 ; X64-NEXT: xorps %xmm1, %xmm1
1199 ; X64-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1202 %vecext = extractelement <4 x float> %A, i32 1
1203 %vecinit = insertelement <4 x float> zeroinitializer, float %vecext, i32 1
1204 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 2
1205 ret <4 x float> %vecinit1