1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
4 define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
5 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
7 ; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
10 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
12 ; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
14 %1 = load <16 x i8>, <16 x i8>* %a, align 1
15 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
16 %3 = sext <8 x i8> %2 to <8 x i16>
20 define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
21 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
23 ; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
26 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
28 ; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
30 %1 = load <16 x i8>, <16 x i8>* %a, align 1
31 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
32 %3 = sext <4 x i8> %2 to <4 x i32>
36 define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
37 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
39 ; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
42 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
44 ; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
46 %1 = load <16 x i8>, <16 x i8>* %a, align 1
47 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
48 %3 = sext <2 x i8> %2 to <2 x i64>
52 define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
53 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
55 ; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
58 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
60 ; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
62 %1 = load <8 x i16>, <8 x i16>* %a, align 1
63 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
64 %3 = sext <4 x i16> %2 to <4 x i32>
68 define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
69 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
71 ; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
74 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
76 ; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
78 %1 = load <8 x i16>, <8 x i16>* %a, align 1
79 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
80 %3 = sext <2 x i16> %2 to <2 x i64>
84 define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
85 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
87 ; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
90 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
92 ; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
94 %1 = load <4 x i32>, <4 x i32>* %a, align 1
95 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
96 %3 = sext <2 x i32> %2 to <2 x i64>
100 define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
101 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
103 ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
106 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
108 ; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
110 %1 = load <16 x i8>, <16 x i8>* %a, align 1
111 %2 = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %1)
115 define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
116 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
118 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
121 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
123 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
125 %1 = load <16 x i8>, <16 x i8>* %a, align 1
126 %2 = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %1)
130 define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
131 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
133 ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
136 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
138 ; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
140 %1 = load <16 x i8>, <16 x i8>* %a, align 1
141 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %1)
145 define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
146 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
148 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
151 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
153 ; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
155 %1 = load <8 x i16>, <8 x i16>* %a, align 1
156 %2 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %1)
160 define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
161 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
163 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
166 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
168 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
170 %1 = load <8 x i16>, <8 x i16>* %a, align 1
171 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %1)
175 define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
176 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
178 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
181 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
183 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
185 %1 = load <4 x i32>, <4 x i32>* %a, align 1
186 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %1)
190 declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>)
191 declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>)
192 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>)
193 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>)
194 declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>)
195 declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>)