1 ; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=SSE -check-prefix=CHECK
2 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX -check-prefix=CHECK
4 ; Test ADDSUB ISel patterns.
6 ; Functions below are obtained from the following source:
8 ; typedef double double2 __attribute__((ext_vector_type(2)));
9 ; typedef double double4 __attribute__((ext_vector_type(4)));
10 ; typedef float float4 __attribute__((ext_vector_type(4)));
11 ; typedef float float8 __attribute__((ext_vector_type(8)));
13 ; float4 test1(float4 A, float4 B) {
16 ; return (float4){X[0], Y[1], X[2], Y[3]};
19 ; float8 test2(float8 A, float8 B) {
22 ; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
25 ; double4 test3(double4 A, double4 B) {
28 ; return (double4){X[0], Y[1], X[2], Y[3]};
31 ; double2 test4(double2 A, double2 B) {
34 ; return (double2){X[0], Y[1]};
37 define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
38 %sub = fsub <4 x float> %A, %B
39 %add = fadd <4 x float> %A, %B
40 %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
41 ret <4 x float> %vecinit6
49 define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
50 %sub = fsub <8 x float> %A, %B
51 %add = fadd <8 x float> %A, %B
52 %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
53 ret <8 x float> %vecinit14
63 define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
64 %sub = fsub <4 x double> %A, %B
65 %add = fadd <4 x double> %A, %B
66 %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
67 ret <4 x double> %vecinit6
77 define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
78 %add = fadd <2 x double> %A, %B
79 %sub = fsub <2 x double> %A, %B
80 %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
81 ret <2 x double> %vecinit2
89 define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
90 %1 = load <4 x float>* %B
91 %add = fadd <4 x float> %A, %1
92 %sub = fsub <4 x float> %A, %1
93 %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
94 ret <4 x float> %vecinit6
102 define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
103 %1 = load <8 x float>* %B
104 %add = fadd <8 x float> %A, %1
105 %sub = fsub <8 x float> %A, %1
106 %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
107 ret <8 x float> %vecinit14
109 ; CHECK-LABEL: test2b
117 define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
118 %1 = load <4 x double>* %B
119 %add = fadd <4 x double> %A, %1
120 %sub = fsub <4 x double> %A, %1
121 %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
122 ret <4 x double> %vecinit6
124 ; CHECK-LABEL: test3b
132 define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
133 %1 = load <2 x double>* %B
134 %sub = fsub <2 x double> %A, %1
135 %add = fadd <2 x double> %A, %1
136 %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
137 ret <2 x double> %vecinit2
139 ; CHECK-LABEL: test4b