1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s
3 ; SSE2 Logical Shift Left
5 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
6 ; CHECK-LABEL: test_sllw_1:
7 ; CHECK: # BB#0: # %entry
10 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
14 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
15 ; CHECK-LABEL: test_sllw_2:
16 ; CHECK: # BB#0: # %entry
17 ; CHECK-NEXT: paddw %xmm0, %xmm0
20 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
24 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
25 ; CHECK-LABEL: test_sllw_3:
26 ; CHECK: # BB#0: # %entry
27 ; CHECK-NEXT: psllw $15, %xmm0
30 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
34 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
35 ; CHECK-LABEL: test_slld_1:
36 ; CHECK: # BB#0: # %entry
39 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
43 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
44 ; CHECK-LABEL: test_slld_2:
45 ; CHECK: # BB#0: # %entry
46 ; CHECK-NEXT: paddd %xmm0, %xmm0
49 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
53 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
54 ; CHECK-LABEL: test_slld_3:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: pslld $31, %xmm0
59 %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
63 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
64 ; CHECK-LABEL: test_sllq_1:
65 ; CHECK: # BB#0: # %entry
68 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
72 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
73 ; CHECK-LABEL: test_sllq_2:
74 ; CHECK: # BB#0: # %entry
75 ; CHECK-NEXT: paddq %xmm0, %xmm0
78 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
82 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
83 ; CHECK-LABEL: test_sllq_3:
84 ; CHECK: # BB#0: # %entry
85 ; CHECK-NEXT: psllq $63, %xmm0
88 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
92 ; SSE2 Arithmetic Shift
94 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
95 ; CHECK-LABEL: test_sraw_1:
96 ; CHECK: # BB#0: # %entry
99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
103 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
104 ; CHECK-LABEL: test_sraw_2:
105 ; CHECK: # BB#0: # %entry
106 ; CHECK-NEXT: psraw $1, %xmm0
109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
113 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
114 ; CHECK-LABEL: test_sraw_3:
115 ; CHECK: # BB#0: # %entry
116 ; CHECK-NEXT: psraw $15, %xmm0
119 %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
123 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
124 ; CHECK-LABEL: test_srad_1:
125 ; CHECK: # BB#0: # %entry
128 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
132 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
133 ; CHECK-LABEL: test_srad_2:
134 ; CHECK: # BB#0: # %entry
135 ; CHECK-NEXT: psrad $1, %xmm0
138 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
142 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
143 ; CHECK-LABEL: test_srad_3:
144 ; CHECK: # BB#0: # %entry
145 ; CHECK-NEXT: psrad $31, %xmm0
148 %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
152 ; SSE Logical Shift Right
154 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
155 ; CHECK-LABEL: test_srlw_1:
156 ; CHECK: # BB#0: # %entry
159 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
163 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
164 ; CHECK-LABEL: test_srlw_2:
165 ; CHECK: # BB#0: # %entry
166 ; CHECK-NEXT: psrlw $1, %xmm0
169 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
173 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
174 ; CHECK-LABEL: test_srlw_3:
175 ; CHECK: # BB#0: # %entry
176 ; CHECK-NEXT: psrlw $15, %xmm0
179 %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
183 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
184 ; CHECK-LABEL: test_srld_1:
185 ; CHECK: # BB#0: # %entry
188 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
192 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
193 ; CHECK-LABEL: test_srld_2:
194 ; CHECK: # BB#0: # %entry
195 ; CHECK-NEXT: psrld $1, %xmm0
198 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
202 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
203 ; CHECK-LABEL: test_srld_3:
204 ; CHECK: # BB#0: # %entry
205 ; CHECK-NEXT: psrld $31, %xmm0
208 %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
212 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
213 ; CHECK-LABEL: test_srlq_1:
214 ; CHECK: # BB#0: # %entry
217 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
221 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
222 ; CHECK-LABEL: test_srlq_2:
223 ; CHECK: # BB#0: # %entry
224 ; CHECK-NEXT: psrlq $1, %xmm0
227 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
231 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
232 ; CHECK-LABEL: test_srlq_3:
233 ; CHECK: # BB#0: # %entry
234 ; CHECK-NEXT: psrlq $63, %xmm0
237 %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>
241 define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind {
242 ; CHECK-LABEL: sra_sra_v4i32:
244 ; CHECK-NEXT: psrad $6, %xmm0
246 %sra0 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
247 %sra1 = ashr <4 x i32> %sra0, <i32 4, i32 4, i32 4, i32 4>
251 define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind {
252 ; CHECK-LABEL: srl_srl_v4i32:
254 ; CHECK-NEXT: psrld $6, %xmm0
256 %srl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
257 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
261 define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind {
262 ; CHECK-LABEL: srl_shl_v4i32:
264 ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
266 %srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
267 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
271 define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
272 ; CHECK-LABEL: srl_sra_31_v4i32:
274 ; CHECK-NEXT: psrld $31, %xmm0
276 %sra = ashr <4 x i32> %x, %y
277 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
281 define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind {
282 ; CHECK-LABEL: shl_shl_v4i32:
284 ; CHECK-NEXT: pslld $6, %xmm0
286 %shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
287 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
291 define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind {
292 ; CHECK-LABEL: shl_sra_v4i32:
294 ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
296 %shl0 = ashr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
297 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
301 define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind {
302 ; CHECK-LABEL: shl_srl_v4i32:
304 ; CHECK-NEXT: pslld $3, %xmm0
305 ; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
307 %shl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
308 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
312 define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind {
313 ; CHECK-LABEL: shl_zext_srl_v4i32:
315 ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
316 ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
318 %srl = lshr <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
319 %zext = zext <4 x i16> %srl to <4 x i32>
320 %shl = shl <4 x i32> %zext, <i32 2, i32 2, i32 2, i32 2>
324 define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind {
325 ; CHECK-LABEL: sra_trunc_srl_v4i32:
327 ; CHECK-NEXT: psrad $19, %xmm0
329 %srl = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
330 %trunc = trunc <4 x i32> %srl to <4 x i16>
331 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
335 define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind {
336 ; CHECK-LABEL: shl_zext_shl_v4i32:
338 ; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
339 ; CHECK-NEXT: pslld $19, %xmm0
341 %shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
342 %ext = zext <4 x i16> %shl0 to <4 x i32>
343 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
347 define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind {
348 ; CHECK-LABEL: sra_v4i32:
350 ; CHECK-NEXT: psrad $3, %xmm0
352 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
356 define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind {
357 ; CHECK-LABEL: srl_v4i32:
359 ; CHECK-NEXT: psrld $3, %xmm0
361 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
365 define <4 x i32> @shl_v4i32(<4 x i32> %x) nounwind {
366 ; CHECK-LABEL: shl_v4i32:
368 ; CHECK-NEXT: pslld $3, %xmm0
370 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>