1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
3 define <4 x i3> @test1(<4 x i3>* %in) nounwind {
6 ; CHECK-NEXT: movzwl (%rdi), %eax
7 ; CHECK-NEXT: movl %eax, %ecx
8 ; CHECK-NEXT: shrl $3, %ecx
9 ; CHECK-NEXT: andl $7, %ecx
10 ; CHECK-NEXT: movl %eax, %edx
11 ; CHECK-NEXT: andl $7, %edx
12 ; CHECK-NEXT: vmovd %edx, %xmm0
13 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
14 ; CHECK-NEXT: movl %eax, %ecx
15 ; CHECK-NEXT: shrl $6, %ecx
16 ; CHECK-NEXT: andl $7, %ecx
17 ; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
18 ; CHECK-NEXT: shrl $9, %eax
19 ; CHECK-NEXT: andl $7, %eax
20 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
22 %ret = load <4 x i3>, <4 x i3>* %in, align 1
26 define <4 x i1> @test2(<4 x i1>* %in) nounwind {
29 ; CHECK-NEXT: movzbl (%rdi), %eax
30 ; CHECK-NEXT: movl %eax, %ecx
31 ; CHECK-NEXT: shrl %ecx
32 ; CHECK-NEXT: andl $1, %ecx
33 ; CHECK-NEXT: movl %eax, %edx
34 ; CHECK-NEXT: andl $1, %edx
35 ; CHECK-NEXT: vmovd %edx, %xmm0
36 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
37 ; CHECK-NEXT: movl %eax, %ecx
38 ; CHECK-NEXT: shrl $2, %ecx
39 ; CHECK-NEXT: andl $1, %ecx
40 ; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
41 ; CHECK-NEXT: shrl $3, %eax
42 ; CHECK-NEXT: andl $1, %eax
43 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
45 %ret = load <4 x i1>, <4 x i1>* %in, align 1
49 define <4 x i64> @test3(<4 x i1>* %in) nounwind {
52 ; CHECK-NEXT: movzbl (%rdi), %eax
53 ; CHECK-NEXT: movq %rax, %rcx
54 ; CHECK-NEXT: shlq $62, %rcx
55 ; CHECK-NEXT: sarq $63, %rcx
56 ; CHECK-NEXT: movq %rax, %rdx
57 ; CHECK-NEXT: shlq $63, %rdx
58 ; CHECK-NEXT: sarq $63, %rdx
59 ; CHECK-NEXT: vmovd %edx, %xmm0
60 ; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
61 ; CHECK-NEXT: movq %rax, %rcx
62 ; CHECK-NEXT: shlq $61, %rcx
63 ; CHECK-NEXT: sarq $63, %rcx
64 ; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
65 ; CHECK-NEXT: shlq $60, %rax
66 ; CHECK-NEXT: sarq $63, %rax
67 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
68 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
69 ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
70 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
71 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
73 %wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
74 %sext = sext <4 x i1> %wide.load35 to <4 x i64>
78 define <16 x i4> @test4(<16 x i4>* %in) nounwind {
81 ; CHECK-NEXT: movq (%rdi), %rax
82 ; CHECK-NEXT: movl %eax, %ecx
83 ; CHECK-NEXT: shrl $4, %ecx
84 ; CHECK-NEXT: andl $15, %ecx
85 ; CHECK-NEXT: movl %eax, %edx
86 ; CHECK-NEXT: andl $15, %edx
87 ; CHECK-NEXT: vmovd %edx, %xmm0
88 ; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
89 ; CHECK-NEXT: movl %eax, %ecx
90 ; CHECK-NEXT: shrl $8, %ecx
91 ; CHECK-NEXT: andl $15, %ecx
92 ; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0
93 ; CHECK-NEXT: movl %eax, %ecx
94 ; CHECK-NEXT: shrl $12, %ecx
95 ; CHECK-NEXT: andl $15, %ecx
96 ; CHECK-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
97 ; CHECK-NEXT: movl %eax, %ecx
98 ; CHECK-NEXT: shrl $16, %ecx
99 ; CHECK-NEXT: andl $15, %ecx
100 ; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
101 ; CHECK-NEXT: movl %eax, %ecx
102 ; CHECK-NEXT: shrl $20, %ecx
103 ; CHECK-NEXT: andl $15, %ecx
104 ; CHECK-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0
105 ; CHECK-NEXT: movl %eax, %ecx
106 ; CHECK-NEXT: shrl $24, %ecx
107 ; CHECK-NEXT: andl $15, %ecx
108 ; CHECK-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0
109 ; CHECK-NEXT: movl %eax, %ecx
110 ; CHECK-NEXT: shrl $28, %ecx
111 ; CHECK-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
112 ; CHECK-NEXT: movq %rax, %rcx
113 ; CHECK-NEXT: shrq $32, %rcx
114 ; CHECK-NEXT: andl $15, %ecx
115 ; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
116 ; CHECK-NEXT: movq %rax, %rcx
117 ; CHECK-NEXT: shrq $36, %rcx
118 ; CHECK-NEXT: andl $15, %ecx
119 ; CHECK-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0
120 ; CHECK-NEXT: movq %rax, %rcx
121 ; CHECK-NEXT: shrq $40, %rcx
122 ; CHECK-NEXT: andl $15, %ecx
123 ; CHECK-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0
124 ; CHECK-NEXT: movq %rax, %rcx
125 ; CHECK-NEXT: shrq $44, %rcx
126 ; CHECK-NEXT: andl $15, %ecx
127 ; CHECK-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
128 ; CHECK-NEXT: movq %rax, %rcx
129 ; CHECK-NEXT: shrq $48, %rcx
130 ; CHECK-NEXT: andl $15, %ecx
131 ; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
132 ; CHECK-NEXT: movq %rax, %rcx
133 ; CHECK-NEXT: shrq $52, %rcx
134 ; CHECK-NEXT: andl $15, %ecx
135 ; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
136 ; CHECK-NEXT: movq %rax, %rcx
137 ; CHECK-NEXT: shrq $56, %rcx
138 ; CHECK-NEXT: andl $15, %ecx
139 ; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
140 ; CHECK-NEXT: shrq $60, %rax
141 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
143 %ret = load <16 x i4>, <16 x i4>* %in, align 1