1 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=knl < %s | FileCheck %s -check-prefix=AVX512
2 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
3 ; RUN: opt -mtriple=x86_64-apple-darwin -codegenprepare -mcpu=corei7-avx -S < %s | FileCheck %s -check-prefix=AVX_SCALAR
4 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=skx < %s | FileCheck %s -check-prefix=SKX
7 ; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z}
10 ; AVX2: vpmaskmovd {{.*}}(%rdi)
11 ; AVX2: vpmaskmovd {{.*}}(%rdi)
14 ; AVX_SCALAR-LABEL: test1
15 ; AVX_SCALAR-NOT: masked
16 ; AVX_SCALAR: extractelement
17 ; AVX_SCALAR: insertelement
18 ; AVX_SCALAR: extractelement
19 ; AVX_SCALAR: insertelement
20 define <16 x i32> @test1(<16 x i32> %trigger, <16 x i32>* %addr) {
21 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
22 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef)
27 ; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z}
30 ; AVX2: vpmaskmovd {{.*}}(%rdi)
31 ; AVX2: vpmaskmovd {{.*}}(%rdi)
33 define <16 x i32> @test2(<16 x i32> %trigger, <16 x i32>* %addr) {
34 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
35 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer)
40 ; AVX512: vmovdqu32 %zmm1, (%rdi) {%k1}
42 ; AVX_SCALAR-LABEL: test3
43 ; AVX_SCALAR-NOT: masked
44 ; AVX_SCALAR: extractelement
46 ; AVX_SCALAR: extractelement
48 ; AVX_SCALAR: extractelement
50 define void @test3(<16 x i32> %trigger, <16 x i32>* %addr, <16 x i32> %val) {
51 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
57 ; AVX512: vmovups (%rdi), %zmm{{.*{%k[1-7]}}}
60 ; AVX2: vmaskmovps {{.*}}(%rdi)
61 ; AVX2: vmaskmovps {{.*}}(%rdi)
63 define <16 x float> @test4(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %dst) {
64 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
65 %res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst)
70 ; AVX512: vmovupd (%rdi), %zmm1 {%k1}
77 define <8 x double> @test5(<8 x i32> %trigger, <8 x double>* %addr, <8 x double> %dst) {
78 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
79 %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst)
88 ; SKX: vmovupd {{.*}}{%k1}
89 define <2 x double> @test6(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {
90 %mask = icmp eq <2 x i64> %trigger, zeroinitializer
91 %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
96 ; AVX2: vmaskmovps {{.*}}(%rdi)
100 ; SKX: vmovups (%rdi){{.*}}{%k1}
101 define <4 x float> @test7(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %dst) {
102 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
103 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)
108 ; AVX2: vpmaskmovd {{.*}}(%rdi)
112 ; SKX: vmovdqu32 (%rdi){{.*}}{%k1}
113 define <4 x i32> @test8(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
114 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
115 %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
120 ; AVX2: vpmaskmovd %xmm
123 ; SKX: vmovdqu32 %xmm{{.*}}{%k1}
124 define void @test9(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
125 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
126 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
131 ; AVX2: vmaskmovpd (%rdi), %ymm
135 ; SKX: vmovapd {{.*}}{%k1}
136 define <4 x double> @test10(<4 x i32> %trigger, <4 x double>* %addr, <4 x double> %dst) {
137 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
138 %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 32, <4 x i1>%mask, <4 x double>%dst)
139 ret <4 x double> %res
147 ; SKX: vmovaps {{.*}}{%k1}
148 define <8 x float> @test11(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {
149 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
150 %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 32, <8 x i1>%mask, <8 x float>%dst)
155 ; AVX2: vpmaskmovd %ymm
158 ; SKX: vmovdqu32 {{.*}}{%k1}
159 define void @test12(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) {
160 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
161 call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)
165 ; AVX512-LABEL: test13
166 ; AVX512: vmovups %zmm1, (%rdi) {%k1}
168 define void @test13(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %val) {
169 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
170 call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)
182 ; SKX: vmovups {{.*}}{%k1}
184 define void @test14(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
185 %mask = icmp eq <2 x i32> %trigger, zeroinitializer
186 call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)
195 ; SKX-NEXT: vpxor %xmm2, %xmm2, %xmm2
196 ; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
197 ; SKX-NEXT: vpcmpeqq %xmm2, %xmm0, %k1
198 ; SKX-NEXT: vpmovqd %xmm1, (%rdi) {%k1}
200 define void @test15(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
201 %mask = icmp eq <2 x i32> %trigger, zeroinitializer
202 call void @llvm.masked.store.v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)
213 ; SKX: vmovups {{.*}}{%k1}
214 define <2 x float> @test16(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) {
215 %mask = icmp eq <2 x i32> %trigger, zeroinitializer
216 %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)
228 ; SKX: vmovdqu32 {{.*}}{%k1}
229 define <2 x i32> @test17(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {
230 %mask = icmp eq <2 x i32> %trigger, zeroinitializer
231 %res = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)
239 define <2 x float> @test18(<2 x i32> %trigger, <2 x float>* %addr) {
240 %mask = icmp eq <2 x i32> %trigger, zeroinitializer
241 %res = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>undef)
245 ; AVX_SCALAR-LABEL: test19
246 ; AVX_SCALAR: load <4 x float>, <4 x float>* %addr, align 4
248 define <4 x float> @test19(<4 x i32> %trigger, <4 x float>* %addr) {
249 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
250 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>, <4 x float>undef)
254 ; AVX_SCALAR-LABEL: test20
255 ; AVX_SCALAR: load float, {{.*}}, align 4
256 ; AVX_SCALAR: insertelement <4 x float> undef, float
257 ; AVX_SCALAR: select <4 x i1> <i1 true, i1 false, i1 true, i1 true>
259 define <4 x float> @test20(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %src0) {
260 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
261 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 16, <4 x i1><i1 true, i1 false, i1 true, i1 true>, <4 x float> %src0)
265 ; AVX_SCALAR-LABEL: test21
266 ; AVX_SCALAR: store <4 x i32> %val
267 define void @test21(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
268 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
269 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>)
273 ; AVX_SCALAR-LABEL: test22
274 ; AVX_SCALAR: extractelement <4 x i32> %val, i32 0
275 ; AVX_SCALAR: store i32
276 define void @test22(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
277 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
278 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>)
282 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
283 declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
284 declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)
285 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
286 declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
287 declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
288 declare void @llvm.masked.store.v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)
289 declare void @llvm.masked.store.v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
290 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
291 declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>)
292 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
293 declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
294 declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)
295 declare <2 x float> @llvm.masked.load.v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)
296 declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)
297 declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
298 declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
299 declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
300 declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
301 declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)