1 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=knl < %s | FileCheck %s -check-prefix=AVX512
2 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
5 ; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z}
8 ; AVX2: vpmaskmovd 32(%rdi)
9 ; AVX2: vpmaskmovd (%rdi)
12 define <16 x i32> @test1(<16 x i32> %trigger, <16 x i32>* %addr) {
13 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
14 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef)
19 ; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z}
22 ; AVX2: vpmaskmovd {{.*}}(%rdi)
23 ; AVX2: vpmaskmovd {{.*}}(%rdi)
25 define <16 x i32> @test2(<16 x i32> %trigger, <16 x i32>* %addr) {
26 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
27 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer)
32 ; AVX512: vmovdqu32 %zmm1, (%rdi) {%k1}
34 define void @test3(<16 x i32> %trigger, <16 x i32>* %addr, <16 x i32> %val) {
35 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
36 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
41 ; AVX512: vmovups (%rdi), %zmm{{.*{%k[1-7]}}}
44 ; AVX2: vmaskmovps {{.*}}(%rdi)
45 ; AVX2: vmaskmovps {{.*}}(%rdi)
47 define <16 x float> @test4(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %dst) {
48 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
49 %res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst)
54 ; AVX512: vmovupd (%rdi), %zmm1 {%k1}
61 define <8 x double> @test5(<8 x i32> %trigger, <8 x double>* %addr, <8 x double> %dst) {
62 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
63 %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst)
70 define <2 x double> @test6(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {
71 %mask = icmp eq <2 x i64> %trigger, zeroinitializer
72 %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
77 ; AVX2: vmaskmovps {{.*}}(%rdi)
79 define <4 x float> @test7(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %dst) {
80 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
81 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)
86 ; AVX2: vpmaskmovd {{.*}}(%rdi)
88 define <4 x i32> @test8(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
89 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
90 %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
95 ; AVX2: vpmaskmovd %xmm
96 define void @test9(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
97 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
98 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
103 ; AVX2: vmaskmovpd (%rdi), %ymm
105 define <4 x double> @test10(<4 x i32> %trigger, <4 x double>* %addr, <4 x double> %dst) {
106 %mask = icmp eq <4 x i32> %trigger, zeroinitializer
107 %res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1>%mask, <4 x double>%dst)
108 ret <4 x double> %res
114 define <8 x float> @test11(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {
115 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
116 %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)
121 ; AVX2: vpmaskmovd %ymm
122 define void @test12(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) {
123 %mask = icmp eq <8 x i32> %trigger, zeroinitializer
124 call void @llvm.masked.store.v8i32(<8 x i32>%val, <8 x i32>* %addr, i32 4, <8 x i1>%mask)
128 ; AVX512-LABEL: test13
129 ; AVX512: vmovups %zmm1, (%rdi) {%k1}
131 define void @test13(<16 x i32> %trigger, <16 x float>* %addr, <16 x float> %val) {
132 %mask = icmp eq <16 x i32> %trigger, zeroinitializer
133 call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)
137 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
138 declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
139 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
140 declare void @llvm.masked.store.v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
141 declare void @llvm.masked.store.v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
142 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
143 declare void @llvm.masked.store.v16f32p(<16 x float>*, <16 x float>**, i32, <16 x i1>)
144 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
145 declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
146 declare <4 x float> @llvm.masked.load.v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)
147 declare <8 x double> @llvm.masked.load.v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)
148 declare <4 x double> @llvm.masked.load.v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
149 declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
150 declare void @llvm.masked.store.v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
151 declare void @llvm.masked.store.v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
152 declare void @llvm.masked.store.v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)