1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE3
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3,+ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSSE3
3 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
4 ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
8 define <4 x float> @hadd_ps_test1(<4 x float> %A, <4 x float> %B) {
9 %vecext = extractelement <4 x float> %A, i32 0
10 %vecext1 = extractelement <4 x float> %A, i32 1
11 %add = fadd float %vecext, %vecext1
12 %vecinit = insertelement <4 x float> undef, float %add, i32 0
13 %vecext2 = extractelement <4 x float> %A, i32 2
14 %vecext3 = extractelement <4 x float> %A, i32 3
15 %add4 = fadd float %vecext2, %vecext3
16 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
17 %vecext6 = extractelement <4 x float> %B, i32 0
18 %vecext7 = extractelement <4 x float> %B, i32 1
19 %add8 = fadd float %vecext6, %vecext7
20 %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
21 %vecext10 = extractelement <4 x float> %B, i32 2
22 %vecext11 = extractelement <4 x float> %B, i32 3
23 %add12 = fadd float %vecext10, %vecext11
24 %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
25 ret <4 x float> %vecinit13
27 ; CHECK-LABEL: hadd_ps_test1
32 define <4 x float> @hadd_ps_test2(<4 x float> %A, <4 x float> %B) {
33 %vecext = extractelement <4 x float> %A, i32 2
34 %vecext1 = extractelement <4 x float> %A, i32 3
35 %add = fadd float %vecext, %vecext1
36 %vecinit = insertelement <4 x float> undef, float %add, i32 1
37 %vecext2 = extractelement <4 x float> %A, i32 0
38 %vecext3 = extractelement <4 x float> %A, i32 1
39 %add4 = fadd float %vecext2, %vecext3
40 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 0
41 %vecext6 = extractelement <4 x float> %B, i32 2
42 %vecext7 = extractelement <4 x float> %B, i32 3
43 %add8 = fadd float %vecext6, %vecext7
44 %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 3
45 %vecext10 = extractelement <4 x float> %B, i32 0
46 %vecext11 = extractelement <4 x float> %B, i32 1
47 %add12 = fadd float %vecext10, %vecext11
48 %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 2
49 ret <4 x float> %vecinit13
51 ; CHECK-LABEL: hadd_ps_test2
56 define <4 x float> @hsub_ps_test1(<4 x float> %A, <4 x float> %B) {
57 %vecext = extractelement <4 x float> %A, i32 0
58 %vecext1 = extractelement <4 x float> %A, i32 1
59 %sub = fsub float %vecext, %vecext1
60 %vecinit = insertelement <4 x float> undef, float %sub, i32 0
61 %vecext2 = extractelement <4 x float> %A, i32 2
62 %vecext3 = extractelement <4 x float> %A, i32 3
63 %sub4 = fsub float %vecext2, %vecext3
64 %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 1
65 %vecext6 = extractelement <4 x float> %B, i32 0
66 %vecext7 = extractelement <4 x float> %B, i32 1
67 %sub8 = fsub float %vecext6, %vecext7
68 %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 2
69 %vecext10 = extractelement <4 x float> %B, i32 2
70 %vecext11 = extractelement <4 x float> %B, i32 3
71 %sub12 = fsub float %vecext10, %vecext11
72 %vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 3
73 ret <4 x float> %vecinit13
75 ; CHECK-LABEL: hsub_ps_test1
80 define <4 x float> @hsub_ps_test2(<4 x float> %A, <4 x float> %B) {
81 %vecext = extractelement <4 x float> %A, i32 2
82 %vecext1 = extractelement <4 x float> %A, i32 3
83 %sub = fsub float %vecext, %vecext1
84 %vecinit = insertelement <4 x float> undef, float %sub, i32 1
85 %vecext2 = extractelement <4 x float> %A, i32 0
86 %vecext3 = extractelement <4 x float> %A, i32 1
87 %sub4 = fsub float %vecext2, %vecext3
88 %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 0
89 %vecext6 = extractelement <4 x float> %B, i32 3
90 %vecext7 = extractelement <4 x float> %B, i32 2
91 %sub8 = fsub float %vecext6, %vecext7
92 %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 3
93 %vecext10 = extractelement <4 x float> %B, i32 1
94 %vecext11 = extractelement <4 x float> %B, i32 0
95 %sub12 = fsub float %vecext10, %vecext11
96 %vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2
97 ret <4 x float> %vecinit13
99 ; CHECK-LABEL: hsub_ps_test2
104 define <4 x i32> @phadd_d_test1(<4 x i32> %A, <4 x i32> %B) {
105 %vecext = extractelement <4 x i32> %A, i32 0
106 %vecext1 = extractelement <4 x i32> %A, i32 1
107 %add = add i32 %vecext, %vecext1
108 %vecinit = insertelement <4 x i32> undef, i32 %add, i32 0
109 %vecext2 = extractelement <4 x i32> %A, i32 2
110 %vecext3 = extractelement <4 x i32> %A, i32 3
111 %add4 = add i32 %vecext2, %vecext3
112 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %add4, i32 1
113 %vecext6 = extractelement <4 x i32> %B, i32 0
114 %vecext7 = extractelement <4 x i32> %B, i32 1
115 %add8 = add i32 %vecext6, %vecext7
116 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %add8, i32 2
117 %vecext10 = extractelement <4 x i32> %B, i32 2
118 %vecext11 = extractelement <4 x i32> %B, i32 3
119 %add12 = add i32 %vecext10, %vecext11
120 %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %add12, i32 3
121 ret <4 x i32> %vecinit13
123 ; CHECK-LABEL: phadd_d_test1
131 define <4 x i32> @phadd_d_test2(<4 x i32> %A, <4 x i32> %B) {
132 %vecext = extractelement <4 x i32> %A, i32 2
133 %vecext1 = extractelement <4 x i32> %A, i32 3
134 %add = add i32 %vecext, %vecext1
135 %vecinit = insertelement <4 x i32> undef, i32 %add, i32 1
136 %vecext2 = extractelement <4 x i32> %A, i32 0
137 %vecext3 = extractelement <4 x i32> %A, i32 1
138 %add4 = add i32 %vecext2, %vecext3
139 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %add4, i32 0
140 %vecext6 = extractelement <4 x i32> %B, i32 2
141 %vecext7 = extractelement <4 x i32> %B, i32 3
142 %add8 = add i32 %vecext6, %vecext7
143 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %add8, i32 3
144 %vecext10 = extractelement <4 x i32> %B, i32 0
145 %vecext11 = extractelement <4 x i32> %B, i32 1
146 %add12 = add i32 %vecext10, %vecext11
147 %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %add12, i32 2
148 ret <4 x i32> %vecinit13
150 ; CHECK-LABEL: phadd_d_test2
158 define <4 x i32> @phsub_d_test1(<4 x i32> %A, <4 x i32> %B) {
159 %vecext = extractelement <4 x i32> %A, i32 0
160 %vecext1 = extractelement <4 x i32> %A, i32 1
161 %sub = sub i32 %vecext, %vecext1
162 %vecinit = insertelement <4 x i32> undef, i32 %sub, i32 0
163 %vecext2 = extractelement <4 x i32> %A, i32 2
164 %vecext3 = extractelement <4 x i32> %A, i32 3
165 %sub4 = sub i32 %vecext2, %vecext3
166 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 1
167 %vecext6 = extractelement <4 x i32> %B, i32 0
168 %vecext7 = extractelement <4 x i32> %B, i32 1
169 %sub8 = sub i32 %vecext6, %vecext7
170 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 2
171 %vecext10 = extractelement <4 x i32> %B, i32 2
172 %vecext11 = extractelement <4 x i32> %B, i32 3
173 %sub12 = sub i32 %vecext10, %vecext11
174 %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3
175 ret <4 x i32> %vecinit13
177 ; CHECK-LABEL: phsub_d_test1
185 define <4 x i32> @phsub_d_test2(<4 x i32> %A, <4 x i32> %B) {
186 %vecext = extractelement <4 x i32> %A, i32 2
187 %vecext1 = extractelement <4 x i32> %A, i32 3
188 %sub = sub i32 %vecext, %vecext1
189 %vecinit = insertelement <4 x i32> undef, i32 %sub, i32 1
190 %vecext2 = extractelement <4 x i32> %A, i32 0
191 %vecext3 = extractelement <4 x i32> %A, i32 1
192 %sub4 = sub i32 %vecext2, %vecext3
193 %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 0
194 %vecext6 = extractelement <4 x i32> %B, i32 3
195 %vecext7 = extractelement <4 x i32> %B, i32 2
196 %sub8 = sub i32 %vecext6, %vecext7
197 %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 3
198 %vecext10 = extractelement <4 x i32> %B, i32 1
199 %vecext11 = extractelement <4 x i32> %B, i32 0
200 %sub12 = sub i32 %vecext10, %vecext11
201 %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 2
202 ret <4 x i32> %vecinit13
204 ; CHECK-LABEL: phsub_d_test2
212 define <2 x double> @hadd_pd_test1(<2 x double> %A, <2 x double> %B) {
213 %vecext = extractelement <2 x double> %A, i32 0
214 %vecext1 = extractelement <2 x double> %A, i32 1
215 %add = fadd double %vecext, %vecext1
216 %vecinit = insertelement <2 x double> undef, double %add, i32 0
217 %vecext2 = extractelement <2 x double> %B, i32 0
218 %vecext3 = extractelement <2 x double> %B, i32 1
219 %add2 = fadd double %vecext2, %vecext3
220 %vecinit2 = insertelement <2 x double> %vecinit, double %add2, i32 1
221 ret <2 x double> %vecinit2
223 ; CHECK-LABEL: hadd_pd_test1
228 define <2 x double> @hadd_pd_test2(<2 x double> %A, <2 x double> %B) {
229 %vecext = extractelement <2 x double> %A, i32 1
230 %vecext1 = extractelement <2 x double> %A, i32 0
231 %add = fadd double %vecext, %vecext1
232 %vecinit = insertelement <2 x double> undef, double %add, i32 0
233 %vecext2 = extractelement <2 x double> %B, i32 1
234 %vecext3 = extractelement <2 x double> %B, i32 0
235 %add2 = fadd double %vecext2, %vecext3
236 %vecinit2 = insertelement <2 x double> %vecinit, double %add2, i32 1
237 ret <2 x double> %vecinit2
239 ; CHECK-LABEL: hadd_pd_test2
244 define <2 x double> @hsub_pd_test1(<2 x double> %A, <2 x double> %B) {
245 %vecext = extractelement <2 x double> %A, i32 0
246 %vecext1 = extractelement <2 x double> %A, i32 1
247 %sub = fsub double %vecext, %vecext1
248 %vecinit = insertelement <2 x double> undef, double %sub, i32 0
249 %vecext2 = extractelement <2 x double> %B, i32 0
250 %vecext3 = extractelement <2 x double> %B, i32 1
251 %sub2 = fsub double %vecext2, %vecext3
252 %vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 1
253 ret <2 x double> %vecinit2
255 ; CHECK-LABEL: hsub_pd_test1
260 define <2 x double> @hsub_pd_test2(<2 x double> %A, <2 x double> %B) {
261 %vecext = extractelement <2 x double> %A, i32 1
262 %vecext1 = extractelement <2 x double> %A, i32 0
263 %sub = fsub double %vecext, %vecext1
264 %vecinit = insertelement <2 x double> undef, double %sub, i32 0
265 %vecext2 = extractelement <2 x double> %B, i32 1
266 %vecext3 = extractelement <2 x double> %B, i32 0
267 %sub2 = fsub double %vecext2, %vecext3
268 %vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 1
269 ret <2 x double> %vecinit2
271 ; CHECK-LABEL: hsub_pd_test2
276 define <4 x double> @avx_vhadd_pd_test(<4 x double> %A, <4 x double> %B) {
277 %vecext = extractelement <4 x double> %A, i32 0
278 %vecext1 = extractelement <4 x double> %A, i32 1
279 %add = fadd double %vecext, %vecext1
280 %vecinit = insertelement <4 x double> undef, double %add, i32 0
281 %vecext2 = extractelement <4 x double> %A, i32 2
282 %vecext3 = extractelement <4 x double> %A, i32 3
283 %add4 = fadd double %vecext2, %vecext3
284 %vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1
285 %vecext6 = extractelement <4 x double> %B, i32 0
286 %vecext7 = extractelement <4 x double> %B, i32 1
287 %add8 = fadd double %vecext6, %vecext7
288 %vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2
289 %vecext10 = extractelement <4 x double> %B, i32 2
290 %vecext11 = extractelement <4 x double> %B, i32 3
291 %add12 = fadd double %vecext10, %vecext11
292 %vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3
293 ret <4 x double> %vecinit13
295 ; CHECK-LABEL: avx_vhadd_pd_test
305 define <4 x double> @avx_vhsub_pd_test(<4 x double> %A, <4 x double> %B) {
306 %vecext = extractelement <4 x double> %A, i32 0
307 %vecext1 = extractelement <4 x double> %A, i32 1
308 %sub = fsub double %vecext, %vecext1
309 %vecinit = insertelement <4 x double> undef, double %sub, i32 0
310 %vecext2 = extractelement <4 x double> %A, i32 2
311 %vecext3 = extractelement <4 x double> %A, i32 3
312 %sub4 = fsub double %vecext2, %vecext3
313 %vecinit5 = insertelement <4 x double> %vecinit, double %sub4, i32 1
314 %vecext6 = extractelement <4 x double> %B, i32 0
315 %vecext7 = extractelement <4 x double> %B, i32 1
316 %sub8 = fsub double %vecext6, %vecext7
317 %vecinit9 = insertelement <4 x double> %vecinit5, double %sub8, i32 2
318 %vecext10 = extractelement <4 x double> %B, i32 2
319 %vecext11 = extractelement <4 x double> %B, i32 3
320 %sub12 = fsub double %vecext10, %vecext11
321 %vecinit13 = insertelement <4 x double> %vecinit9, double %sub12, i32 3
322 ret <4 x double> %vecinit13
324 ; CHECK-LABEL: avx_vhsub_pd_test
334 define <8 x i32> @avx2_vphadd_d_test(<8 x i32> %A, <8 x i32> %B) {
335 %vecext = extractelement <8 x i32> %A, i32 0
336 %vecext1 = extractelement <8 x i32> %A, i32 1
337 %add = add i32 %vecext, %vecext1
338 %vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
339 %vecext2 = extractelement <8 x i32> %A, i32 2
340 %vecext3 = extractelement <8 x i32> %A, i32 3
341 %add4 = add i32 %vecext2, %vecext3
342 %vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 1
343 %vecext6 = extractelement <8 x i32> %A, i32 4
344 %vecext7 = extractelement <8 x i32> %A, i32 5
345 %add8 = add i32 %vecext6, %vecext7
346 %vecinit9 = insertelement <8 x i32> %vecinit5, i32 %add8, i32 2
347 %vecext10 = extractelement <8 x i32> %A, i32 6
348 %vecext11 = extractelement <8 x i32> %A, i32 7
349 %add12 = add i32 %vecext10, %vecext11
350 %vecinit13 = insertelement <8 x i32> %vecinit9, i32 %add12, i32 3
351 %vecext14 = extractelement <8 x i32> %B, i32 0
352 %vecext15 = extractelement <8 x i32> %B, i32 1
353 %add16 = add i32 %vecext14, %vecext15
354 %vecinit17 = insertelement <8 x i32> %vecinit13, i32 %add16, i32 4
355 %vecext18 = extractelement <8 x i32> %B, i32 2
356 %vecext19 = extractelement <8 x i32> %B, i32 3
357 %add20 = add i32 %vecext18, %vecext19
358 %vecinit21 = insertelement <8 x i32> %vecinit17, i32 %add20, i32 5
359 %vecext22 = extractelement <8 x i32> %B, i32 4
360 %vecext23 = extractelement <8 x i32> %B, i32 5
361 %add24 = add i32 %vecext22, %vecext23
362 %vecinit25 = insertelement <8 x i32> %vecinit21, i32 %add24, i32 6
363 %vecext26 = extractelement <8 x i32> %B, i32 6
364 %vecext27 = extractelement <8 x i32> %B, i32 7
365 %add28 = add i32 %vecext26, %vecext27
366 %vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
367 ret <8 x i32> %vecinit29
369 ; CHECK-LABEL: avx2_vphadd_d_test