now that generic vector types aren't selected onto MMX registers, these
[oota-llvm.git] / test / CodeGen / X86 / fast-isel-atomic.ll
1 ; RUN: llc < %s -O0 -march=x86-64
2 ; rdar://8204072
3 ; PR7652
4
5 @sc = external global i8
6 @uc = external global i8
7
8 declare i8 @llvm.atomic.load.and.i8.p0i8(i8* nocapture, i8) nounwind
9
10 define void @test_fetch_and_op() nounwind {
11 entry:
12   %tmp40 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
13   store i8 %tmp40, i8* @sc
14   %tmp41 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
15   store i8 %tmp41, i8* @uc
16   ret void
17 }