1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
3 ; Verify that the DAGCombiner correctly folds according to the following rules:
5 ; fold (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
6 ; fold (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
7 ; fold (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
9 ; fold (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
10 ; fold (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
11 ; fold (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
15 define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
16 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
17 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
18 %and = and <4 x i32> %shuf1, %shuf2
28 define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
29 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
30 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
31 %or = or <4 x i32> %shuf1, %shuf2
41 define <4 x i32> @test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
42 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
43 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
44 %xor = xor <4 x i32> %shuf1, %shuf2
54 define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
55 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
56 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
57 %and = and <4 x i32> %shuf1, %shuf2
67 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
68 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
69 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
70 %or = or <4 x i32> %shuf1, %shuf2
80 define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
81 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
82 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
83 %xor = xor <4 x i32> %shuf1, %shuf2
93 ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
94 ; are not performing a swizzle operations.
96 define <4 x i32> @test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
97 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
98 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
99 %and = and <4 x i32> %shuf1, %shuf2
102 ; CHECK-LABEL: test1b
105 ; CHECK-NEXT: blendps
109 define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
110 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
111 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
112 %or = or <4 x i32> %shuf1, %shuf2
115 ; CHECK-LABEL: test2b
118 ; CHECK-NEXT: blendps
122 define <4 x i32> @test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
123 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
124 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
125 %xor = xor <4 x i32> %shuf1, %shuf2
128 ; CHECK-LABEL: test3b
132 ; CHECK-NEXT: blendps
136 define <4 x i32> @test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
137 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
138 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
139 %and = and <4 x i32> %shuf1, %shuf2
142 ; CHECK-LABEL: test4b
145 ; CHECK-NEXT: blendps
149 define <4 x i32> @test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
150 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
151 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
152 %or = or <4 x i32> %shuf1, %shuf2
155 ; CHECK-LABEL: test5b
158 ; CHECK-NEXT: blendps
162 define <4 x i32> @test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
163 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
164 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
165 %xor = xor <4 x i32> %shuf1, %shuf2
168 ; CHECK-LABEL: test6b
172 ; CHECK-NEXT: blendps
175 define <4 x i32> @test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
176 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
177 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
178 %and = and <4 x i32> %shuf1, %shuf2
181 ; CHECK-LABEL: test1c
188 define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
189 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
190 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
191 %or = or <4 x i32> %shuf1, %shuf2
194 ; CHECK-LABEL: test2c
201 define <4 x i32> @test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
202 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
203 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
204 %xor = xor <4 x i32> %shuf1, %shuf2
207 ; CHECK-LABEL: test3c
215 define <4 x i32> @test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
216 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
217 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
218 %and = and <4 x i32> %shuf1, %shuf2
221 ; CHECK-LABEL: test4c
228 define <4 x i32> @test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
229 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
230 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
231 %or = or <4 x i32> %shuf1, %shuf2
234 ; CHECK-LABEL: test5c
241 define <4 x i32> @test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
242 %shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
243 %shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
244 %xor = xor <4 x i32> %shuf1, %shuf2
247 ; CHECK-LABEL: test6c