1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
4 ; Verify that each of the following test cases is folded into a single
5 ; instruction which performs a blend operation.
7 define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) {
10 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
12 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
13 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
14 %or = or <2 x i64> %shuf1, %shuf2
19 define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {
22 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
24 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
25 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
26 %or = or <4 x i32> %shuf1, %shuf2
31 define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {
34 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
36 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
37 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
38 %or = or <2 x i64> %shuf1, %shuf2
43 define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
46 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
48 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
49 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
50 %or = or <4 x i32> %shuf1, %shuf2
55 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
58 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
60 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
61 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
62 %or = or <4 x i32> %shuf1, %shuf2
67 define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) {
70 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
72 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
73 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
74 %or = or <4 x i32> %shuf1, %shuf2
79 define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) {
82 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
84 %and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
85 %and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1>
86 %or = or <4 x i32> %and1, %and2
91 define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) {
94 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
96 %and1 = and <2 x i64> %a, <i64 -1, i64 0>
97 %and2 = and <2 x i64> %b, <i64 0, i64 -1>
98 %or = or <2 x i64> %and1, %and2
103 define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {
104 ; CHECK-LABEL: test9:
106 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
108 %and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
109 %and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0>
110 %or = or <4 x i32> %and1, %and2
115 define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {
116 ; CHECK-LABEL: test10:
118 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
120 %and1 = and <2 x i64> %a, <i64 0, i64 -1>
121 %and2 = and <2 x i64> %b, <i64 -1, i64 0>
122 %or = or <2 x i64> %and1, %and2
127 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
128 ; CHECK-LABEL: test11:
130 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
132 %and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
133 %and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1>
134 %or = or <4 x i32> %and1, %and2
139 define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
140 ; CHECK-LABEL: test12:
142 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
144 %and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1>
145 %and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0>
146 %or = or <4 x i32> %and1, %and2
151 ; Verify that the following test cases are folded into single shuffles.
153 define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
154 ; CHECK-LABEL: test13:
156 ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
158 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
159 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
160 %or = or <4 x i32> %shuf1, %shuf2
165 define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
166 ; CHECK-LABEL: test14:
168 ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
170 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
171 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
172 %or = or <2 x i64> %shuf1, %shuf2
177 define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
178 ; CHECK-LABEL: test15:
180 ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1]
181 ; CHECK-NEXT: movaps %xmm1, %xmm0
183 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
184 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
185 %or = or <4 x i32> %shuf1, %shuf2
190 define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
191 ; CHECK-LABEL: test16:
193 ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
194 ; CHECK-NEXT: movdqa %xmm1, %xmm0
196 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
197 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
198 %or = or <2 x i64> %shuf1, %shuf2
203 ; Verify that the dag-combiner does not fold a OR of two shuffles into a single
204 ; shuffle instruction when the shuffle indexes are not compatible.
206 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
207 ; CHECK-LABEL: test17:
\r
209 ; CHECK-NEXT: xorps %xmm2, %xmm2
\r
210 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,2]
\r
211 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
\r
212 ; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm1[0],zero
\r
213 ; CHECK-NEXT: orps %xmm2, %xmm0
\r
215 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
\r
216 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
\r
217 %or = or <4 x i32> %shuf1, %shuf2
222 define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
223 ; CHECK-LABEL: test18:
225 ; CHECK-NEXT: pxor %xmm2, %xmm2
226 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
227 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
228 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
229 ; CHECK-NEXT: por %xmm1, %xmm0
231 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
232 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
233 %or = or <4 x i32> %shuf1, %shuf2
238 define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
239 ; CHECK-LABEL: test19:
241 ; CHECK-NEXT: xorps %xmm2, %xmm2
242 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,3]
243 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
244 ; CHECK-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm1[2,2]
245 ; CHECK-NEXT: orps %xmm1, %xmm2
246 ; CHECK-NEXT: movaps %xmm2, %xmm0
248 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
249 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
250 %or = or <4 x i32> %shuf1, %shuf2
255 define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
256 ; CHECK-LABEL: test20:
258 ; CHECK-NEXT: orps %xmm1, %xmm0
259 ; CHECK-NEXT: movq %xmm0, %xmm0
261 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
262 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
263 %or = or <2 x i64> %shuf1, %shuf2
268 define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
269 ; CHECK-LABEL: test21:
271 ; CHECK-NEXT: por %xmm1, %xmm0
272 ; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
274 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
275 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
276 %or = or <2 x i64> %shuf1, %shuf2
280 ; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
281 ; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
282 ; handle legal vector value types.
283 define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) {
284 ; CHECK-LABEL: test_crash:
286 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
288 %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
289 %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
290 %or = or <4 x i8> %shuf1, %shuf2