1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
3 ; Verify that the DAGCombiner is able to fold a vector AND into a blend
4 ; if one of the operands to the AND is a vector of all constants, and each
5 ; constant element is either zero or all-ones.
8 define <4 x i32> @test1(<4 x i32> %A) {
9 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0>
13 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
17 define <4 x i32> @test2(<4 x i32> %A) {
18 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0>
22 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
26 define <4 x i32> @test3(<4 x i32> %A) {
27 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0>
31 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
35 define <4 x i32> @test4(<4 x i32> %A) {
36 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>
40 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
44 define <4 x i32> @test5(<4 x i32> %A) {
45 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
49 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
53 define <4 x i32> @test6(<4 x i32> %A) {
54 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
58 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
62 define <4 x i32> @test7(<4 x i32> %A) {
63 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1>
67 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
71 define <4 x i32> @test8(<4 x i32> %A) {
72 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1>
76 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
80 define <4 x i32> @test9(<4 x i32> %A) {
81 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0>
85 ; CHECK: movq %xmm0, %xmm0
89 define <4 x i32> @test10(<4 x i32> %A) {
90 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0>
94 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
98 define <4 x i32> @test11(<4 x i32> %A) {
99 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1>
102 ; CHECK-LABEL: test11
103 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
107 define <4 x i32> @test12(<4 x i32> %A) {
108 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0>
111 ; CHECK-LABEL: test12
112 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
116 define <4 x i32> @test13(<4 x i32> %A) {
117 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1>
120 ; CHECK-LABEL: test13
121 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
125 define <4 x i32> @test14(<4 x i32> %A) {
126 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
129 ; CHECK-LABEL: test14
130 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
134 define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
135 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>
136 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0>
137 %3 = or <4 x i32> %1, %2
140 ; CHECK-LABEL: test15
141 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
145 define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
146 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>
147 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1>
148 %3 = or <4 x i32> %1, %2
151 ; CHECK-LABEL: test16
152 ; CHECK: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
156 define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
157 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>
158 %2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0>
159 %3 = or <4 x i32> %1, %2
162 ; CHECK-LABEL: test17
163 ; CHECK: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]