1 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
3 define i32 @t1(i32 %x) nounwind {
4 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
13 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
15 define i32 @t2(i32 %x) nounwind {
16 %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
24 declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
26 define i16 @t3(i16 %x, i16 %y) nounwind {
28 %tmp1 = add i16 %x, %y
29 %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; <i16> [#uses=1]
38 declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
40 define i32 @t4(i32 %n) nounwind {
42 ; Generate a cmov to handle zero inputs when necessary.
48 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false)
52 define i32 @t5(i32 %n) nounwind {
54 ; Don't generate the cmovne when the source is known non-zero (and bsr would
63 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 false)
67 define i32 @t6(i32 %n) nounwind {
69 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
70 ; the most significant bit, which is what 'bsr' does natively.
75 %ctlz = tail call i32 @llvm.ctlz.i32(i32 %n, i1 true)
76 %bsr = xor i32 %ctlz, 31
80 define i32 @t7(i32 %n) nounwind {
82 ; Same as t6, but ensure this happens even when there is a potential zero.
87 %ctlz = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false)
88 %bsr = xor i32 %ctlz, 31