1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s
4 define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
6 ; CHECK: ## BB#0: ## %entry
7 ; CHECK-NEXT: vpbroadcastb (%rdi), %xmm0
10 %q = load i8, i8* %ptr, align 4
11 %q0 = insertelement <16 x i8> undef, i8 %q, i32 0
12 %q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
13 %q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
14 %q3 = insertelement <16 x i8> %q2, i8 %q, i32 3
15 %q4 = insertelement <16 x i8> %q3, i8 %q, i32 4
16 %q5 = insertelement <16 x i8> %q4, i8 %q, i32 5
17 %q6 = insertelement <16 x i8> %q5, i8 %q, i32 6
18 %q7 = insertelement <16 x i8> %q6, i8 %q, i32 7
19 %q8 = insertelement <16 x i8> %q7, i8 %q, i32 8
20 %q9 = insertelement <16 x i8> %q8, i8 %q, i32 9
21 %qa = insertelement <16 x i8> %q9, i8 %q, i32 10
22 %qb = insertelement <16 x i8> %qa, i8 %q, i32 11
23 %qc = insertelement <16 x i8> %qb, i8 %q, i32 12
24 %qd = insertelement <16 x i8> %qc, i8 %q, i32 13
25 %qe = insertelement <16 x i8> %qd, i8 %q, i32 14
26 %qf = insertelement <16 x i8> %qe, i8 %q, i32 15
30 define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
32 ; CHECK: ## BB#0: ## %entry
33 ; CHECK-NEXT: vpbroadcastb (%rdi), %ymm0
36 %q = load i8, i8* %ptr, align 4
37 %q0 = insertelement <32 x i8> undef, i8 %q, i32 0
38 %q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
39 %q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
40 %q3 = insertelement <32 x i8> %q2, i8 %q, i32 3
41 %q4 = insertelement <32 x i8> %q3, i8 %q, i32 4
42 %q5 = insertelement <32 x i8> %q4, i8 %q, i32 5
43 %q6 = insertelement <32 x i8> %q5, i8 %q, i32 6
44 %q7 = insertelement <32 x i8> %q6, i8 %q, i32 7
45 %q8 = insertelement <32 x i8> %q7, i8 %q, i32 8
46 %q9 = insertelement <32 x i8> %q8, i8 %q, i32 9
47 %qa = insertelement <32 x i8> %q9, i8 %q, i32 10
48 %qb = insertelement <32 x i8> %qa, i8 %q, i32 11
49 %qc = insertelement <32 x i8> %qb, i8 %q, i32 12
50 %qd = insertelement <32 x i8> %qc, i8 %q, i32 13
51 %qe = insertelement <32 x i8> %qd, i8 %q, i32 14
52 %qf = insertelement <32 x i8> %qe, i8 %q, i32 15
54 %q20 = insertelement <32 x i8> %qf, i8 %q, i32 16
55 %q21 = insertelement <32 x i8> %q20, i8 %q, i32 17
56 %q22 = insertelement <32 x i8> %q21, i8 %q, i32 18
57 %q23 = insertelement <32 x i8> %q22, i8 %q, i32 19
58 %q24 = insertelement <32 x i8> %q23, i8 %q, i32 20
59 %q25 = insertelement <32 x i8> %q24, i8 %q, i32 21
60 %q26 = insertelement <32 x i8> %q25, i8 %q, i32 22
61 %q27 = insertelement <32 x i8> %q26, i8 %q, i32 23
62 %q28 = insertelement <32 x i8> %q27, i8 %q, i32 24
63 %q29 = insertelement <32 x i8> %q28, i8 %q, i32 25
64 %q2a = insertelement <32 x i8> %q29, i8 %q, i32 26
65 %q2b = insertelement <32 x i8> %q2a, i8 %q, i32 27
66 %q2c = insertelement <32 x i8> %q2b, i8 %q, i32 28
67 %q2d = insertelement <32 x i8> %q2c, i8 %q, i32 29
68 %q2e = insertelement <32 x i8> %q2d, i8 %q, i32 30
69 %q2f = insertelement <32 x i8> %q2e, i8 %q, i32 31
73 define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
75 ; CHECK: ## BB#0: ## %entry
76 ; CHECK-NEXT: vpbroadcastw (%rdi), %xmm0
79 %q = load i16, i16* %ptr, align 4
80 %q0 = insertelement <8 x i16> undef, i16 %q, i32 0
81 %q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
82 %q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
83 %q3 = insertelement <8 x i16> %q2, i16 %q, i32 3
84 %q4 = insertelement <8 x i16> %q3, i16 %q, i32 4
85 %q5 = insertelement <8 x i16> %q4, i16 %q, i32 5
86 %q6 = insertelement <8 x i16> %q5, i16 %q, i32 6
87 %q7 = insertelement <8 x i16> %q6, i16 %q, i32 7
91 define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
93 ; CHECK: ## BB#0: ## %entry
94 ; CHECK-NEXT: vpbroadcastw (%rdi), %ymm0
97 %q = load i16, i16* %ptr, align 4
98 %q0 = insertelement <16 x i16> undef, i16 %q, i32 0
99 %q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
100 %q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
101 %q3 = insertelement <16 x i16> %q2, i16 %q, i32 3
102 %q4 = insertelement <16 x i16> %q3, i16 %q, i32 4
103 %q5 = insertelement <16 x i16> %q4, i16 %q, i32 5
104 %q6 = insertelement <16 x i16> %q5, i16 %q, i32 6
105 %q7 = insertelement <16 x i16> %q6, i16 %q, i32 7
106 %q8 = insertelement <16 x i16> %q7, i16 %q, i32 8
107 %q9 = insertelement <16 x i16> %q8, i16 %q, i32 9
108 %qa = insertelement <16 x i16> %q9, i16 %q, i32 10
109 %qb = insertelement <16 x i16> %qa, i16 %q, i32 11
110 %qc = insertelement <16 x i16> %qb, i16 %q, i32 12
111 %qd = insertelement <16 x i16> %qc, i16 %q, i32 13
112 %qe = insertelement <16 x i16> %qd, i16 %q, i32 14
113 %qf = insertelement <16 x i16> %qe, i16 %q, i32 15
117 define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
119 ; CHECK: ## BB#0: ## %entry
120 ; CHECK-NEXT: vbroadcastss (%rdi), %xmm0
123 %q = load i32, i32* %ptr, align 4
124 %q0 = insertelement <4 x i32> undef, i32 %q, i32 0
125 %q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
126 %q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
127 %q3 = insertelement <4 x i32> %q2, i32 %q, i32 3
131 define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
133 ; CHECK: ## BB#0: ## %entry
134 ; CHECK-NEXT: vbroadcastss (%rdi), %ymm0
137 %q = load i32, i32* %ptr, align 4
138 %q0 = insertelement <8 x i32> undef, i32 %q, i32 0
139 %q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
140 %q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
141 %q3 = insertelement <8 x i32> %q2, i32 %q, i32 3
142 %q4 = insertelement <8 x i32> %q3, i32 %q, i32 4
143 %q5 = insertelement <8 x i32> %q4, i32 %q, i32 5
144 %q6 = insertelement <8 x i32> %q5, i32 %q, i32 6
145 %q7 = insertelement <8 x i32> %q6, i32 %q, i32 7
149 define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
151 ; CHECK: ## BB#0: ## %entry
152 ; CHECK-NEXT: vpbroadcastq (%rdi), %xmm0
155 %q = load i64, i64* %ptr, align 4
156 %q0 = insertelement <2 x i64> undef, i64 %q, i32 0
157 %q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
161 define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
163 ; CHECK: ## BB#0: ## %entry
164 ; CHECK-NEXT: vbroadcastsd (%rdi), %ymm0
167 %q = load i64, i64* %ptr, align 4
168 %q0 = insertelement <4 x i64> undef, i64 %q, i32 0
169 %q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
170 %q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
171 %q3 = insertelement <4 x i64> %q2, i64 %q, i32 3
175 ; make sure that we still don't support broadcast double into 128-bit vector
177 define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
179 ; CHECK: ## BB#0: ## %entry
180 ; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
183 %q = load double, double* %ptr, align 4
184 %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
185 %vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
186 ret <2 x double> %vecinit2.i
189 define <8 x i32> @V111(<8 x i32> %in) nounwind uwtable readnone ssp {
191 ; CHECK: ## BB#0: ## %entry
192 ; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
193 ; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
196 %g = add <8 x i32> %in, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
200 define <8 x float> @V113(<8 x float> %in) nounwind uwtable readnone ssp {
202 ; CHECK: ## BB#0: ## %entry
203 ; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
204 ; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0
207 %g = fadd <8 x float> %in, <float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000>
211 define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
214 ; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %xmm0
216 %vecinit.i = insertelement <4 x float> undef, float 0xbf80000000000000, i32 0
217 %vecinit2.i = insertelement <4 x float> %vecinit.i, float 0xbf80000000000000, i32 1
218 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
219 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
220 ret <4 x float> %vecinit6.i
223 define <8 x i8> @_e4(i8* %ptr) nounwind uwtable readnone ssp {
226 ; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [52,52,52,52,52,52,52,52]
228 %vecinit0.i = insertelement <8 x i8> undef, i8 52, i32 0
229 %vecinit1.i = insertelement <8 x i8> %vecinit0.i, i8 52, i32 1
230 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 52, i32 2
231 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 52, i32 3
232 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 52, i32 4
233 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 52, i32 5
234 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 52, i32 6
235 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 52, i32 7
236 ret <8 x i8> %vecinit7.i
240 define void @crash() nounwind alwaysinline {
241 ; CHECK-LABEL: crash:
242 ; CHECK: ## BB#0: ## %WGLoopsEntry
243 ; CHECK-NEXT: xorl %eax, %eax
244 ; CHECK-NEXT: testb %al, %al
245 ; CHECK-NEXT: je LBB13_1
246 ; CHECK-NEXT: ## BB#2: ## %ret
248 ; CHECK-NEXT: .align 4, 0x90
249 ; CHECK-NEXT: LBB13_1: ## %footer349VF
250 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
251 ; CHECK-NEXT: jmp LBB13_1
253 br i1 undef, label %ret, label %footer329VF
256 %A.0.inVF = fmul float undef, 6.553600e+04
257 %B.0.in407VF = fmul <8 x float> undef, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>
258 %A.0VF = fptosi float %A.0.inVF to i32
259 %B.0408VF = fptosi <8 x float> %B.0.in407VF to <8 x i32>
260 %0 = and <8 x i32> %B.0408VF, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
261 %1 = and i32 %A.0VF, 65535
262 %temp1098VF = insertelement <8 x i32> undef, i32 %1, i32 0
263 %vector1099VF = shufflevector <8 x i32> %temp1098VF, <8 x i32> undef, <8 x i32> zeroinitializer
264 br i1 undef, label %preload1201VF, label %footer349VF
267 br label %footer349VF
270 %2 = mul nsw <8 x i32> undef, %0
271 %3 = mul nsw <8 x i32> undef, %vector1099VF
272 br label %footer329VF
278 define <8 x i32> @_inreg0(i32 %scalar) nounwind uwtable readnone ssp {
279 ; CHECK-LABEL: _inreg0:
281 ; CHECK-NEXT: vmovd %edi, %xmm0
282 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
284 %in = insertelement <8 x i32> undef, i32 %scalar, i32 0
285 %wide = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer
289 define <8 x float> @_inreg1(float %scalar) nounwind uwtable readnone ssp {
290 ; CHECK-LABEL: _inreg1:
292 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
294 %in = insertelement <8 x float> undef, float %scalar, i32 0
295 %wide = shufflevector <8 x float> %in, <8 x float> undef, <8 x i32> zeroinitializer
296 ret <8 x float> %wide
299 define <4 x float> @_inreg2(float %scalar) nounwind uwtable readnone ssp {
300 ; CHECK-LABEL: _inreg2:
302 ; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
304 %in = insertelement <4 x float> undef, float %scalar, i32 0
305 %wide = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> zeroinitializer
306 ret <4 x float> %wide
309 define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp {
310 ; CHECK-LABEL: _inreg3:
312 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
314 %in = insertelement <4 x double> undef, double %scalar, i32 0
315 %wide = shufflevector <4 x double> %in, <4 x double> undef, <4 x i32> zeroinitializer
316 ret <4 x double> %wide
319 define <8 x float> @_inreg8xfloat(<8 x float> %a) {
320 ; CHECK-LABEL: _inreg8xfloat:
322 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
324 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
328 define <4 x float> @_inreg4xfloat(<4 x float> %a) {
329 ; CHECK-LABEL: _inreg4xfloat:
331 ; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
333 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
337 define <16 x i16> @_inreg16xi16(<16 x i16> %a) {
338 ; CHECK-LABEL: _inreg16xi16:
340 ; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
342 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
346 define <8 x i16> @_inreg8xi16(<8 x i16> %a) {
347 ; CHECK-LABEL: _inreg8xi16:
349 ; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
351 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
355 define <4 x i64> @_inreg4xi64(<4 x i64> %a) {
356 ; CHECK-LABEL: _inreg4xi64:
358 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
360 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
364 define <2 x i64> @_inreg2xi64(<2 x i64> %a) {
365 ; CHECK-LABEL: _inreg2xi64:
367 ; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
369 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
373 define <4 x double> @_inreg4xdouble(<4 x double> %a) {
374 ; CHECK-LABEL: _inreg4xdouble:
376 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
378 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
382 define <2 x double> @_inreg2xdouble(<2 x double> %a) {
383 ; CHECK-LABEL: _inreg2xdouble:
385 ; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
387 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
391 define <8 x i32> @_inreg8xi32(<8 x i32> %a) {
392 ; CHECK-LABEL: _inreg8xi32:
394 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
396 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
400 define <4 x i32> @_inreg4xi32(<4 x i32> %a) {
401 ; CHECK-LABEL: _inreg4xi32:
403 ; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
405 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
409 define <32 x i8> @_inreg32xi8(<32 x i8> %a) {
410 ; CHECK-LABEL: _inreg32xi8:
412 ; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
414 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
418 define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
419 ; CHECK-LABEL: _inreg16xi8:
421 ; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
423 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
427 ; These tests check that a vbroadcast instruction is used when we have a splat
428 ; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
429 ; (via the insertelements).
431 define <8 x float> @splat_concat1(float %f) {
432 ; CHECK-LABEL: splat_concat1:
434 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
436 %1 = insertelement <4 x float> undef, float %f, i32 0
437 %2 = insertelement <4 x float> %1, float %f, i32 1
438 %3 = insertelement <4 x float> %2, float %f, i32 2
439 %4 = insertelement <4 x float> %3, float %f, i32 3
440 %5 = shufflevector <4 x float> %4, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
444 define <8 x float> @splat_concat2(float %f) {
445 ; CHECK-LABEL: splat_concat2:
447 ; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
449 %1 = insertelement <4 x float> undef, float %f, i32 0
450 %2 = insertelement <4 x float> %1, float %f, i32 1
451 %3 = insertelement <4 x float> %2, float %f, i32 2
452 %4 = insertelement <4 x float> %3, float %f, i32 3
453 %5 = insertelement <4 x float> undef, float %f, i32 0
454 %6 = insertelement <4 x float> %5, float %f, i32 1
455 %7 = insertelement <4 x float> %6, float %f, i32 2
456 %8 = insertelement <4 x float> %7, float %f, i32 3
457 %9 = shufflevector <4 x float> %4, <4 x float> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
461 define <4 x double> @splat_concat3(double %d) {
462 ; CHECK-LABEL: splat_concat3:
464 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
466 %1 = insertelement <2 x double> undef, double %d, i32 0
467 %2 = insertelement <2 x double> %1, double %d, i32 1
468 %3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
472 define <4 x double> @splat_concat4(double %d) {
473 ; CHECK-LABEL: splat_concat4:
475 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
477 %1 = insertelement <2 x double> undef, double %d, i32 0
478 %2 = insertelement <2 x double> %1, double %d, i32 1
479 %3 = insertelement <2 x double> undef, double %d, i32 0
480 %4 = insertelement <2 x double> %3, double %d, i32 1
481 %5 = shufflevector <2 x double> %2, <2 x double> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
485 ; Test cases for <rdar://problem/16074331>.
486 ; Instruction selection for broacast instruction fails if
487 ; the load cannot be folded into the broadcast.
488 ; This happens if the load has initial one use but other uses are
489 ; created later, or if selection DAG cannot prove that folding the
490 ; load will not create a cycle in the DAG.
491 ; Those test cases exerce the latter.
493 ; CHECK-LABEL: isel_crash_16b
494 ; CHECK: vpbroadcastb {{[^,]+}}, %xmm{{[0-9]+}}
496 define void @isel_crash_16b(i8* %cV_R.addr) {
498 %__a.addr.i = alloca <2 x i64>, align 16
499 %__b.addr.i = alloca <2 x i64>, align 16
500 %vCr = alloca <2 x i64>, align 16
501 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
502 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
503 %tmp2 = load i8, i8* %cV_R.addr, align 4
504 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
505 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
506 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
507 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
508 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
512 ; CHECK-LABEL: isel_crash_32b
513 ; CHECK: vpbroadcastb {{[^,]+}}, %ymm{{[0-9]+}}
515 define void @isel_crash_32b(i8* %cV_R.addr) {
517 %__a.addr.i = alloca <4 x i64>, align 16
518 %__b.addr.i = alloca <4 x i64>, align 16
519 %vCr = alloca <4 x i64>, align 16
520 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
521 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
522 %tmp2 = load i8, i8* %cV_R.addr, align 4
523 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
524 %splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitializer
525 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
526 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
527 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
531 ; CHECK-LABEL: isel_crash_8w
532 ; CHECK: vpbroadcastw {{[^,]+}}, %xmm{{[0-9]+}}
534 define void @isel_crash_8w(i16* %cV_R.addr) {
536 %__a.addr.i = alloca <2 x i64>, align 16
537 %__b.addr.i = alloca <2 x i64>, align 16
538 %vCr = alloca <2 x i64>, align 16
539 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
540 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
541 %tmp2 = load i16, i16* %cV_R.addr, align 4
542 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
543 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
544 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
545 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
546 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
550 ; CHECK-LABEL: isel_crash_16w
551 ; CHECK: vpbroadcastw {{[^,]+}}, %ymm{{[0-9]+}}
553 define void @isel_crash_16w(i16* %cV_R.addr) {
555 %__a.addr.i = alloca <4 x i64>, align 16
556 %__b.addr.i = alloca <4 x i64>, align 16
557 %vCr = alloca <4 x i64>, align 16
558 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
559 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
560 %tmp2 = load i16, i16* %cV_R.addr, align 4
561 %splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0
562 %splat.splat = shufflevector <16 x i16> %splat.splatinsert, <16 x i16> undef, <16 x i32> zeroinitializer
563 %tmp3 = bitcast <16 x i16> %splat.splat to <4 x i64>
564 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
565 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
569 ; CHECK-LABEL: isel_crash_4d
570 ; CHECK: vbroadcastss {{[^,]+}}, %xmm{{[0-9]+}}
572 define void @isel_crash_4d(i32* %cV_R.addr) {
574 %__a.addr.i = alloca <2 x i64>, align 16
575 %__b.addr.i = alloca <2 x i64>, align 16
576 %vCr = alloca <2 x i64>, align 16
577 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
578 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
579 %tmp2 = load i32, i32* %cV_R.addr, align 4
580 %splat.splatinsert = insertelement <4 x i32> undef, i32 %tmp2, i32 0
581 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
582 %tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64>
583 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
584 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
588 ; CHECK-LABEL: isel_crash_8d
589 ; CHECK: vbroadcastss {{[^,]+}}, %ymm{{[0-9]+}}
591 define void @isel_crash_8d(i32* %cV_R.addr) {
593 %__a.addr.i = alloca <4 x i64>, align 16
594 %__b.addr.i = alloca <4 x i64>, align 16
595 %vCr = alloca <4 x i64>, align 16
596 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
597 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
598 %tmp2 = load i32, i32* %cV_R.addr, align 4
599 %splat.splatinsert = insertelement <8 x i32> undef, i32 %tmp2, i32 0
600 %splat.splat = shufflevector <8 x i32> %splat.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
601 %tmp3 = bitcast <8 x i32> %splat.splat to <4 x i64>
602 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
603 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
607 ; CHECK-LABEL: isel_crash_2q
608 ; CHECK: vpbroadcastq {{[^,]+}}, %xmm{{[0-9]+}}
610 define void @isel_crash_2q(i64* %cV_R.addr) {
612 %__a.addr.i = alloca <2 x i64>, align 16
613 %__b.addr.i = alloca <2 x i64>, align 16
614 %vCr = alloca <2 x i64>, align 16
615 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
616 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
617 %tmp2 = load i64, i64* %cV_R.addr, align 4
618 %splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0
619 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
620 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
621 store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
625 ; CHECK-LABEL: isel_crash_4q
626 ; CHECK: vbroadcastsd {{[^,]+}}, %ymm{{[0-9]+}}
628 define void @isel_crash_4q(i64* %cV_R.addr) {
630 %__a.addr.i = alloca <4 x i64>, align 16
631 %__b.addr.i = alloca <4 x i64>, align 16
632 %vCr = alloca <4 x i64>, align 16
633 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
634 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
635 %tmp2 = load i64, i64* %cV_R.addr, align 4
636 %splat.splatinsert = insertelement <4 x i64> undef, i64 %tmp2, i32 0
637 %splat.splat = shufflevector <4 x i64> %splat.splatinsert, <4 x i64> undef, <4 x i32> zeroinitializer
638 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
639 store <4 x i64> %splat.splat, <4 x i64>* %__b.addr.i, align 16