1 ; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
5 define i32 @t(i32 %a) nounwind {
7 ; CHECK: asrs r1, r0, #31
9 %tmp0 = ashr i32 %a, 31
10 %tmp1 = xor i32 %tmp0, %a