1 ; Test 32-bit signed division and remainder.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
7 ; Test register division. The result is in the second of the two registers.
8 define void @f1(i32 *%dest, i32 %a, i32 %b) {
10 ; CHECK: lgfr %r1, %r3
11 ; CHECK: dsgfr %r0, %r4
12 ; CHECK: st %r1, 0(%r2)
14 %div = sdiv i32 %a, %b
15 store i32 %div, i32 *%dest
19 ; Test register remainder. The result is in the first of the two registers.
20 define void @f2(i32 *%dest, i32 %a, i32 %b) {
22 ; CHECK: lgfr %r1, %r3
23 ; CHECK: dsgfr %r0, %r4
24 ; CHECK: st %r0, 0(%r2)
26 %rem = srem i32 %a, %b
27 store i32 %rem, i32 *%dest
31 ; Test that division and remainder use a single instruction.
32 define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
35 ; CHECK: lgfr %r3, %r3
37 ; CHECK: dsgfr %r2, %r4
41 %div = sdiv i32 %a, %b
42 %rem = srem i32 %a, %b
43 %or = or i32 %rem, %div
47 ; Check that the sign extension of the dividend is elided when the argument
48 ; is already sign-extended.
49 define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
51 ; CHECK-NOT: {{%r[234]}}
52 ; CHECK: dsgfr %r2, %r4
56 %div = sdiv i32 %a, %b
57 %rem = srem i32 %a, %b
58 %or = or i32 %rem, %div
62 ; Test that memory dividends are loaded using sign extension (LGF).
63 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
66 ; CHECK: lgf %r3, 0(%r3)
68 ; CHECK: dsgfr %r2, %r4
73 %div = sdiv i32 %a, %b
74 %rem = srem i32 %a, %b
75 %or = or i32 %rem, %div
79 ; Test memory division with no displacement.
80 define void @f6(i32 *%dest, i32 %a, i32 *%src) {
82 ; CHECK: lgfr %r1, %r3
83 ; CHECK: dsgf %r0, 0(%r4)
84 ; CHECK: st %r1, 0(%r2)
87 %div = sdiv i32 %a, %b
88 store i32 %div, i32 *%dest
92 ; Test memory remainder with no displacement.
93 define void @f7(i32 *%dest, i32 %a, i32 *%src) {
95 ; CHECK: lgfr %r1, %r3
96 ; CHECK: dsgf %r0, 0(%r4)
97 ; CHECK: st %r0, 0(%r2)
100 %rem = srem i32 %a, %b
101 store i32 %rem, i32 *%dest
105 ; Test both memory division and memory remainder.
106 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
109 ; CHECK: lgfr %r3, %r3
111 ; CHECK: dsgf %r2, 0(%r4)
112 ; CHECK-NOT: {{dsgf|dsgfr}}
116 %div = sdiv i32 %a, %b
117 %rem = srem i32 %a, %b
118 %or = or i32 %rem, %div
122 ; Check the high end of the DSGF range.
123 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
125 ; CHECK: dsgf %r2, 524284(%r4)
127 %ptr = getelementptr i32 *%src, i64 131071
129 %rem = srem i32 %a, %b
133 ; Check the next word up, which needs separate address logic.
134 ; Other sequences besides this one would be OK.
135 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
137 ; CHECK: agfi %r4, 524288
138 ; CHECK: dsgf %r2, 0(%r4)
140 %ptr = getelementptr i32 *%src, i64 131072
142 %rem = srem i32 %a, %b
146 ; Check the high end of the negative aligned DSGF range.
147 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
149 ; CHECK: dsgf %r2, -4(%r4)
151 %ptr = getelementptr i32 *%src, i64 -1
153 %rem = srem i32 %a, %b
157 ; Check the low end of the DSGF range.
158 define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
160 ; CHECK: dsgf %r2, -524288(%r4)
162 %ptr = getelementptr i32 *%src, i64 -131072
164 %rem = srem i32 %a, %b
168 ; Check the next word down, which needs separate address logic.
169 ; Other sequences besides this one would be OK.
170 define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
172 ; CHECK: agfi %r4, -524292
173 ; CHECK: dsgf %r2, 0(%r4)
175 %ptr = getelementptr i32 *%src, i64 -131073
177 %rem = srem i32 %a, %b
181 ; Check that DSGF allows an index.
182 define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
184 ; CHECK: dsgf %r2, 524287(%r5,%r4)
186 %add1 = add i64 %src, %index
187 %add2 = add i64 %add1, 524287
188 %ptr = inttoptr i64 %add2 to i32 *
190 %rem = srem i32 %a, %b
194 ; Make sure that we still use DSGFR rather than DSGR in cases where
195 ; a load and division cannot be combined.
196 define void @f15(i32 *%dest, i32 *%src) {
198 ; CHECK: l [[B:%r[0-9]+]], 0(%r3)
199 ; CHECK: brasl %r14, foo@PLT
200 ; CHECK: lgfr %r1, %r2
201 ; CHECK: dsgfr %r0, [[B]]
205 %div = sdiv i32 %a, %b
206 store i32 %div, i32 *%dest