1 ; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-CHECK -check-prefix=FUNC %s
2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG-CHECK -check-prefix=FUNC %s
3 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM-CHECK -check-prefix=FUNC %s
5 ;===------------------------------------------------------------------------===;
7 ;===------------------------------------------------------------------------===;
8 ; FUNC-LABEL: {{^}}store_i1:
9 ; EG-CHECK: MEM_RAT MSKOR
10 ; SI-CHECK: buffer_store_byte
11 define void @store_i1(i1 addrspace(1)* %out) {
13 store i1 true, i1 addrspace(1)* %out
18 ; EG-CHECK-LABEL: {{^}}store_i8:
19 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
21 ; IG 0: Get the byte index and truncate the value
22 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
23 ; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
24 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
25 ; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43)
28 ; IG 1: Truncate the calculated the shift amount for the mask
30 ; IG 2: Shift the value and the mask
31 ; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
32 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
34 ; IG 3: Initialize the Y and Z channels to zero
35 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
36 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
37 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
39 ; SI-CHECK-LABEL: {{^}}store_i8:
40 ; SI-CHECK: buffer_store_byte
42 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
44 store i8 %in, i8 addrspace(1)* %out
49 ; EG-CHECK-LABEL: {{^}}store_i16:
50 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
52 ; IG 0: Get the byte index and truncate the value
55 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
56 ; EG-CHECK-NEXT: 3(4.203895e-45),
58 ; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
59 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
61 ; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
62 ; IG 1: Truncate the calculated the shift amount for the mask
64 ; IG 2: Shift the value and the mask
65 ; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
66 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
67 ; EG-CHECK-NEXT: 65535
68 ; IG 3: Initialize the Y and Z channels to zero
69 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
70 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
71 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
73 ; SI-CHECK-LABEL: {{^}}store_i16:
74 ; SI-CHECK: buffer_store_short
75 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
77 store i16 %in, i16 addrspace(1)* %out
81 ; EG-CHECK-LABEL: {{^}}store_v2i8:
82 ; EG-CHECK: MEM_RAT MSKOR
83 ; EG-CHECK-NOT: MEM_RAT MSKOR
84 ; SI-CHECK-LABEL: {{^}}store_v2i8:
85 ; SI-CHECK: buffer_store_byte
86 ; SI-CHECK: buffer_store_byte
87 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
89 %0 = trunc <2 x i32> %in to <2 x i8>
90 store <2 x i8> %0, <2 x i8> addrspace(1)* %out
95 ; EG-CHECK-LABEL: {{^}}store_v2i16:
96 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
97 ; CM-CHECK-LABEL: {{^}}store_v2i16:
98 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
99 ; SI-CHECK-LABEL: {{^}}store_v2i16:
100 ; SI-CHECK: buffer_store_short
101 ; SI-CHECK: buffer_store_short
102 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
104 %0 = trunc <2 x i32> %in to <2 x i16>
105 store <2 x i16> %0, <2 x i16> addrspace(1)* %out
109 ; EG-CHECK-LABEL: {{^}}store_v4i8:
110 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
111 ; CM-CHECK-LABEL: {{^}}store_v4i8:
112 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
113 ; SI-CHECK-LABEL: {{^}}store_v4i8:
114 ; SI-CHECK: buffer_store_byte
115 ; SI-CHECK: buffer_store_byte
116 ; SI-CHECK: buffer_store_byte
117 ; SI-CHECK: buffer_store_byte
118 define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
120 %0 = trunc <4 x i32> %in to <4 x i8>
121 store <4 x i8> %0, <4 x i8> addrspace(1)* %out
125 ; floating-point store
126 ; EG-CHECK-LABEL: {{^}}store_f32:
127 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
128 ; CM-CHECK-LABEL: {{^}}store_f32:
129 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
130 ; SI-CHECK-LABEL: {{^}}store_f32:
131 ; SI-CHECK: buffer_store_dword
133 define void @store_f32(float addrspace(1)* %out, float %in) {
134 store float %in, float addrspace(1)* %out
138 ; EG-CHECK-LABEL: {{^}}store_v4i16:
139 ; EG-CHECK: MEM_RAT MSKOR
140 ; EG-CHECK: MEM_RAT MSKOR
141 ; EG-CHECK: MEM_RAT MSKOR
142 ; EG-CHECK: MEM_RAT MSKOR
143 ; EG-CHECK-NOT: MEM_RAT MSKOR
144 ; SI-CHECK-LABEL: {{^}}store_v4i16:
145 ; SI-CHECK: buffer_store_short
146 ; SI-CHECK: buffer_store_short
147 ; SI-CHECK: buffer_store_short
148 ; SI-CHECK: buffer_store_short
149 ; SI-CHECK-NOT: buffer_store_byte
150 define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
152 %0 = trunc <4 x i32> %in to <4 x i16>
153 store <4 x i16> %0, <4 x i16> addrspace(1)* %out
157 ; vec2 floating-point stores
158 ; EG-CHECK-LABEL: {{^}}store_v2f32:
159 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
160 ; CM-CHECK-LABEL: {{^}}store_v2f32:
161 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
162 ; SI-CHECK-LABEL: {{^}}store_v2f32:
163 ; SI-CHECK: buffer_store_dwordx2
165 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
167 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
168 %1 = insertelement <2 x float> %0, float %b, i32 1
169 store <2 x float> %1, <2 x float> addrspace(1)* %out
173 ; EG-CHECK-LABEL: {{^}}store_v4i32:
174 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
175 ; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
176 ; CM-CHECK-LABEL: {{^}}store_v4i32:
177 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
178 ; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
179 ; SI-CHECK-LABEL: {{^}}store_v4i32:
180 ; SI-CHECK: buffer_store_dwordx4
181 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
183 store <4 x i32> %in, <4 x i32> addrspace(1)* %out
187 ; FUNC-LABEL: {{^}}store_i64_i8:
188 ; EG-CHECK: MEM_RAT MSKOR
189 ; SI-CHECK: buffer_store_byte
190 define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
192 %0 = trunc i64 %in to i8
193 store i8 %0, i8 addrspace(1)* %out
197 ; FUNC-LABEL: {{^}}store_i64_i16:
198 ; EG-CHECK: MEM_RAT MSKOR
199 ; SI-CHECK: buffer_store_short
200 define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
202 %0 = trunc i64 %in to i16
203 store i16 %0, i16 addrspace(1)* %out
207 ;===------------------------------------------------------------------------===;
208 ; Local Address Space
209 ;===------------------------------------------------------------------------===;
211 ; FUNC-LABEL: {{^}}store_local_i1:
212 ; EG-CHECK: LDS_BYTE_WRITE
213 ; SI-CHECK: ds_write_b8
214 define void @store_local_i1(i1 addrspace(3)* %out) {
216 store i1 true, i1 addrspace(3)* %out
220 ; EG-CHECK-LABEL: {{^}}store_local_i8:
221 ; EG-CHECK: LDS_BYTE_WRITE
222 ; SI-CHECK-LABEL: {{^}}store_local_i8:
223 ; SI-CHECK: ds_write_b8
224 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
225 store i8 %in, i8 addrspace(3)* %out
229 ; EG-CHECK-LABEL: {{^}}store_local_i16:
230 ; EG-CHECK: LDS_SHORT_WRITE
231 ; SI-CHECK-LABEL: {{^}}store_local_i16:
232 ; SI-CHECK: ds_write_b16
233 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
234 store i16 %in, i16 addrspace(3)* %out
238 ; EG-CHECK-LABEL: {{^}}store_local_v2i16:
239 ; EG-CHECK: LDS_WRITE
240 ; CM-CHECK-LABEL: {{^}}store_local_v2i16:
241 ; CM-CHECK: LDS_WRITE
242 ; SI-CHECK-LABEL: {{^}}store_local_v2i16:
243 ; SI-CHECK: ds_write_b16
244 ; SI-CHECK: ds_write_b16
245 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
247 store <2 x i16> %in, <2 x i16> addrspace(3)* %out
251 ; EG-CHECK-LABEL: {{^}}store_local_v4i8:
252 ; EG-CHECK: LDS_WRITE
253 ; CM-CHECK-LABEL: {{^}}store_local_v4i8:
254 ; CM-CHECK: LDS_WRITE
255 ; SI-CHECK-LABEL: {{^}}store_local_v4i8:
256 ; SI-CHECK: ds_write_b8
257 ; SI-CHECK: ds_write_b8
258 ; SI-CHECK: ds_write_b8
259 ; SI-CHECK: ds_write_b8
260 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) {
262 store <4 x i8> %in, <4 x i8> addrspace(3)* %out
266 ; EG-CHECK-LABEL: {{^}}store_local_v2i32:
267 ; EG-CHECK: LDS_WRITE
268 ; EG-CHECK: LDS_WRITE
269 ; CM-CHECK-LABEL: {{^}}store_local_v2i32:
270 ; CM-CHECK: LDS_WRITE
271 ; CM-CHECK: LDS_WRITE
272 ; SI-CHECK-LABEL: {{^}}store_local_v2i32:
273 ; SI-CHECK: ds_write_b64
274 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
276 store <2 x i32> %in, <2 x i32> addrspace(3)* %out
280 ; EG-CHECK-LABEL: {{^}}store_local_v4i32:
281 ; EG-CHECK: LDS_WRITE
282 ; EG-CHECK: LDS_WRITE
283 ; EG-CHECK: LDS_WRITE
284 ; EG-CHECK: LDS_WRITE
285 ; CM-CHECK-LABEL: {{^}}store_local_v4i32:
286 ; CM-CHECK: LDS_WRITE
287 ; CM-CHECK: LDS_WRITE
288 ; CM-CHECK: LDS_WRITE
289 ; CM-CHECK: LDS_WRITE
290 ; SI-CHECK-LABEL: {{^}}store_local_v4i32:
291 ; SI-CHECK: ds_write_b32
292 ; SI-CHECK: ds_write_b32
293 ; SI-CHECK: ds_write_b32
294 ; SI-CHECK: ds_write_b32
295 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
297 store <4 x i32> %in, <4 x i32> addrspace(3)* %out
301 ; FUNC-LABEL: {{^}}store_local_i64_i8:
302 ; EG-CHECK: LDS_BYTE_WRITE
303 ; SI-CHECK: ds_write_b8
304 define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) {
306 %0 = trunc i64 %in to i8
307 store i8 %0, i8 addrspace(3)* %out
311 ; FUNC-LABEL: {{^}}store_local_i64_i16:
312 ; EG-CHECK: LDS_SHORT_WRITE
313 ; SI-CHECK: ds_write_b16
314 define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) {
316 %0 = trunc i64 %in to i16
317 store i16 %0, i16 addrspace(3)* %out
321 ; The stores in this function are combined by the optimizer to create a
322 ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
323 ; should not try to split the 64-bit store back into 2 32-bit stores.
325 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
326 ; be two 32-bit stores.
328 ; EG-CHECK-LABEL: {{^}}vecload2:
329 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
330 ; CM-CHECK-LABEL: {{^}}vecload2:
331 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
332 ; SI-CHECK-LABEL: {{^}}vecload2:
333 ; SI-CHECK: buffer_store_dwordx2
334 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
336 %0 = load i32 addrspace(2)* %mem, align 4
337 %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
338 %1 = load i32 addrspace(2)* %arrayidx1.i, align 4
339 store i32 %0, i32 addrspace(1)* %out, align 4
340 %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
341 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
345 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
347 ; When i128 was a legal type this program generated cannot select errors:
349 ; FUNC-LABEL: {{^}}"i128-const-store":
350 ; FIXME: We should be able to to this with one store instruction
351 ; EG-CHECK: STORE_RAW
352 ; EG-CHECK: STORE_RAW
353 ; EG-CHECK: STORE_RAW
354 ; EG-CHECK: STORE_RAW
355 ; CM-CHECK: STORE_DWORD
356 ; CM-CHECK: STORE_DWORD
357 ; CM-CHECK: STORE_DWORD
358 ; CM-CHECK: STORE_DWORD
359 ; SI: buffer_store_dwordx2
360 ; SI: buffer_store_dwordx2
361 define void @i128-const-store(i32 addrspace(1)* %out) {
363 store i32 1, i32 addrspace(1)* %out, align 4
364 %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
365 store i32 1, i32 addrspace(1)* %arrayidx2, align 4
366 %arrayidx4 = getelementptr inbounds i32 addrspace(1)* %out, i64 2
367 store i32 2, i32 addrspace(1)* %arrayidx4, align 4
368 %arrayidx6 = getelementptr inbounds i32 addrspace(1)* %out, i64 3
369 store i32 2, i32 addrspace(1)* %arrayidx6, align 4