1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
5 ;EG-CHECK-LABEL: {{^}}ashr_v2i32:
6 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ;SI-CHECK-LABEL: {{^}}ashr_v2i32:
10 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
11 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
13 define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
14 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
15 %a = load <2 x i32> addrspace(1) * %in
16 %b = load <2 x i32> addrspace(1) * %b_ptr
17 %result = ashr <2 x i32> %a, %b
18 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
22 ;EG-CHECK-LABEL: {{^}}ashr_v4i32:
23 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
24 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
26 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ;SI-CHECK-LABEL: {{^}}ashr_v4i32:
29 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
30 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32 ;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
34 define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
35 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
36 %a = load <4 x i32> addrspace(1) * %in
37 %b = load <4 x i32> addrspace(1) * %b_ptr
38 %result = ashr <4 x i32> %a, %b
39 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
43 ;EG-CHECK-LABEL: {{^}}ashr_i64:
46 ;SI-CHECK-LABEL: {{^}}ashr_i64:
47 ;SI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
48 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
50 %0 = sext i32 %in to i64
52 store i64 %1, i64 addrspace(1)* %out
56 ;EG-CHECK-LABEL: {{^}}ashr_i64_2:
57 ;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
58 ;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
59 ;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
60 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
61 ;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
62 ;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
63 ;EG-CHECK-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
64 ;EG-CHECK-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
65 ;EG-CHECK-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
66 ;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
67 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
68 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
70 ;SI-CHECK-LABEL: {{^}}ashr_i64_2:
71 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
72 define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
74 %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
75 %a = load i64 addrspace(1) * %in
76 %b = load i64 addrspace(1) * %b_ptr
77 %result = ashr i64 %a, %b
78 store i64 %result, i64 addrspace(1)* %out
82 ;EG-CHECK-LABEL: {{^}}ashr_v2i64:
83 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
84 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
85 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
86 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
87 ;EG-CHECK-DAG: LSHL {{.*}}, 1
88 ;EG-CHECK-DAG: LSHL {{.*}}, 1
89 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]
90 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]
91 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
92 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
95 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
96 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
99 ;EG-CHECK-DAG: ASHR {{.*}}, literal
100 ;EG-CHECK-DAG: ASHR {{.*}}, literal
101 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
102 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
103 ;EG-CHECK-DAG: CNDE_INT
104 ;EG-CHECK-DAG: CNDE_INT
105 ;EG-CHECK-DAG: CNDE_INT
106 ;EG-CHECK-DAG: CNDE_INT
108 ;SI-CHECK-LABEL: {{^}}ashr_v2i64:
109 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
110 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
112 define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
113 %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
114 %a = load <2 x i64> addrspace(1) * %in
115 %b = load <2 x i64> addrspace(1) * %b_ptr
116 %result = ashr <2 x i64> %a, %b
117 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
121 ;EG-CHECK-LABEL: {{^}}ashr_v4i64:
122 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
123 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
124 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
125 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
126 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
127 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
128 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]]
129 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]]
130 ;EG-CHECK-DAG: LSHL {{.*}}, 1
131 ;EG-CHECK-DAG: LSHL {{.*}}, 1
132 ;EG-CHECK-DAG: LSHL {{.*}}, 1
133 ;EG-CHECK-DAG: LSHL {{.*}}, 1
134 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]
135 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]
136 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHC]]
137 ;EG-CHECK-DAG: ASHR {{.*}}, [[SHD]]
138 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
139 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
140 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
141 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
142 ;EG-CHECK-DAG: OR_INT
143 ;EG-CHECK-DAG: OR_INT
144 ;EG-CHECK-DAG: OR_INT
145 ;EG-CHECK-DAG: OR_INT
146 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
147 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
148 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
149 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
154 ;EG-CHECK-DAG: ASHR {{.*}}, literal
155 ;EG-CHECK-DAG: ASHR {{.*}}, literal
156 ;EG-CHECK-DAG: ASHR {{.*}}, literal
157 ;EG-CHECK-DAG: ASHR {{.*}}, literal
158 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
159 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
160 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
161 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
162 ;EG-CHECK-DAG: CNDE_INT
163 ;EG-CHECK-DAG: CNDE_INT
164 ;EG-CHECK-DAG: CNDE_INT
165 ;EG-CHECK-DAG: CNDE_INT
166 ;EG-CHECK-DAG: CNDE_INT
167 ;EG-CHECK-DAG: CNDE_INT
168 ;EG-CHECK-DAG: CNDE_INT
169 ;EG-CHECK-DAG: CNDE_INT
171 ;SI-CHECK-LABEL: {{^}}ashr_v4i64:
172 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
173 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
174 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
175 ;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
177 define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
178 %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
179 %a = load <4 x i64> addrspace(1) * %in
180 %b = load <4 x i64> addrspace(1) * %b_ptr
181 %result = ashr <4 x i64> %a, %b
182 store <4 x i64> %result, <4 x i64> addrspace(1)* %out