1 ; RUN: llc < %s -march=r600 -mcpu=SI -show-mc-encoding -verify-machineinstrs | FileCheck %s
3 ; SMRD load with an immediate offset.
5 ; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
6 define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
8 %0 = getelementptr i32 addrspace(2)* %ptr, i64 1
9 %1 = load i32 addrspace(2)* %0
10 store i32 %1, i32 addrspace(1)* %out
14 ; SMRD load with the largest possible immediate offset.
16 ; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
17 define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
19 %0 = getelementptr i32 addrspace(2)* %ptr, i64 255
20 %1 = load i32 addrspace(2)* %0
21 store i32 %1, i32 addrspace(1)* %out
25 ; SMRD load with an offset greater than the largest possible immediate.
27 ; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400
28 ; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
30 define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
32 %0 = getelementptr i32 addrspace(2)* %ptr, i64 256
33 %1 = load i32 addrspace(2)* %0
34 store i32 %1, i32 addrspace(1)* %out
38 ; SMRD load with a 64-bit offset
40 ; CHECK-DAG: S_MOV_B32 s[[SLO:[0-9]+]], 0
41 ; CHECK-DAG: S_MOV_B32 s[[SHI:[0-9]+]], 4
42 ; FIXME: We don't need to copy these values to VGPRs
43 ; CHECK-DAG: V_MOV_B32_e32 v[[VLO:[0-9]+]], s[[SLO]]
44 ; CHECK-DAG: V_MOV_B32_e32 v[[VHI:[0-9]+]], s[[SHI]]
45 ; FIXME: We should be able to use S_LOAD_DWORD here
46 ; CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64
48 define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
50 %0 = getelementptr i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32
51 %1 = load i32 addrspace(2)* %0
52 store i32 %1, i32 addrspace(1)* %out
56 ; SMRD load using the load.const intrinsic with an immediate offset
57 ; CHECK-LABEL: @smrd_load_const0
58 ; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
59 define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
61 %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
62 %21 = load <16 x i8> addrspace(2)* %20
63 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
64 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
68 ; SMRD load using the load.const intrinsic with the largest possible immediate
70 ; CHECK-LABEL: @smrd_load_const1
71 ; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
72 define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
74 %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
75 %21 = load <16 x i8> addrspace(2)* %20
76 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020)
77 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
80 ; SMRD load using the load.const intrinsic with an offset greater than the
81 ; largets possible immediate.
83 ; CHECK-LABEL: @smrd_load_const2
84 ; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400
85 ; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
86 define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
88 %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
89 %21 = load <16 x i8> addrspace(2)* %20
90 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024)
91 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
95 ; Function Attrs: nounwind readnone
96 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
98 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
100 attributes #0 = { "ShaderType"="0" }
101 attributes #1 = { nounwind readnone }