1 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone
7 ; FUNC-LABEL: @sext_in_reg_i1_i32
8 ; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
9 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[ARG]], 0, 1
10 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
12 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
13 ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
14 ; EG-NEXT: LSHR * [[ADDR]]
15 define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
16 %shl = shl i32 %in, 31
17 %sext = ashr i32 %shl, 31
18 store i32 %sext, i32 addrspace(1)* %out
22 ; FUNC-LABEL: @sext_in_reg_i8_to_i32
23 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
24 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
25 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
27 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
29 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
30 ; EG-NEXT: LSHR * [[ADDR]]
31 define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
32 %c = add i32 %a, %b ; add to prevent folding into extload
34 %ashr = ashr i32 %shl, 24
35 store i32 %ashr, i32 addrspace(1)* %out, align 4
39 ; FUNC-LABEL: @sext_in_reg_i16_to_i32
40 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
41 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 16
42 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
44 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
46 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
47 ; EG-NEXT: LSHR * [[ADDR]]
48 define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
49 %c = add i32 %a, %b ; add to prevent folding into extload
51 %ashr = ashr i32 %shl, 16
52 store i32 %ashr, i32 addrspace(1)* %out, align 4
56 ; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
57 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
58 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
59 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
61 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
63 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
64 ; EG-NEXT: LSHR * [[ADDR]]
65 define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
66 %c = add <1 x i32> %a, %b ; add to prevent folding into extload
67 %shl = shl <1 x i32> %c, <i32 24>
68 %ashr = ashr <1 x i32> %shl, <i32 24>
69 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
73 ; FUNC-LABEL: @sext_in_reg_i8_to_i64
74 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
75 ; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
76 ; SI: BUFFER_STORE_DWORD
78 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
79 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
81 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
86 ;; TODO Check address computation, using | with variables in {{}} does not work,
87 ;; also the _LO/_HI order might be different
88 define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
91 %ashr = ashr i64 %shl, 56
92 store i64 %ashr, i64 addrspace(1)* %out, align 8
96 ; FUNC-LABEL: @sext_in_reg_i16_to_i64
97 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 16
98 ; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
99 ; SI: BUFFER_STORE_DWORD
101 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
102 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
104 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
105 ; EG: ASHR [[RES_HI]]
109 ;; TODO Check address computation, using | with variables in {{}} does not work,
110 ;; also the _LO/_HI order might be different
111 define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
113 %shl = shl i64 %c, 48
114 %ashr = ashr i64 %shl, 48
115 store i64 %ashr, i64 addrspace(1)* %out, align 8
119 ; FUNC-LABEL: @sext_in_reg_i32_to_i64
122 ; SI: S_ADD_I32 [[ADD:s[0-9]+]],
123 ; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31
124 ; SI: BUFFER_STORE_DWORDX2
126 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
127 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
129 ; EG: ADD_INT {{\*?}} [[RES_LO]]
130 ; EG: ASHR [[RES_HI]]
134 ;; TODO Check address computation, using | with variables in {{}} does not work,
135 ;; also the _LO/_HI order might be different
136 define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
138 %shl = shl i64 %c, 32
139 %ashr = ashr i64 %shl, 32
140 store i64 %ashr, i64 addrspace(1)* %out, align 8
144 ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
145 ; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
146 ; XSI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
147 ; XSI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
148 ; XSI: BUFFER_STORE_DWORD
151 ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
152 ; %c = add <1 x i64> %a, %b
153 ; %shl = shl <1 x i64> %c, <i64 56>
154 ; %ashr = ashr <1 x i64> %shl, <i64 56>
155 ; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
159 ; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
161 ; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
162 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
164 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
169 ; EG: LSHR {{\*?}} [[ADDR]]
170 define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
174 store i32 %y, i32 addrspace(1)* %out
178 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
179 ; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
180 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
181 ; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
182 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
184 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
191 ; EG: LSHR {{\*?}} [[ADDR]]
192 define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
193 %c = add <2 x i32> %a, %b
194 %x = shl <2 x i32> %c, <i32 6, i32 6>
195 %y = ashr <2 x i32> %x, <i32 7, i32 7>
196 store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
201 ; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
202 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
203 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
204 ; SI: BUFFER_STORE_DWORDX2
206 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
207 ; EG: BFE_INT [[RES]]
208 ; EG: BFE_INT [[RES]]
209 ; EG: LSHR {{\*?}} [[ADDR]]
210 define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
211 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
212 %shl = shl <2 x i32> %c, <i32 31, i32 31>
213 %ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
214 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
218 ; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
219 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
220 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
221 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
222 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
223 ; SI: BUFFER_STORE_DWORDX4
225 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
226 ; EG: BFE_INT [[RES]]
227 ; EG: BFE_INT [[RES]]
228 ; EG: BFE_INT [[RES]]
229 ; EG: BFE_INT [[RES]]
230 ; EG: LSHR {{\*?}} [[ADDR]]
231 define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
232 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
233 %shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
234 %ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
235 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
239 ; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
240 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
241 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
242 ; SI: BUFFER_STORE_DWORDX2
244 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
245 ; EG: BFE_INT [[RES]]
246 ; EG: BFE_INT [[RES]]
247 ; EG: LSHR {{\*?}} [[ADDR]]
248 define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
249 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
250 %shl = shl <2 x i32> %c, <i32 24, i32 24>
251 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
252 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
256 ; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
257 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
258 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
259 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
260 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
261 ; SI: BUFFER_STORE_DWORDX4
263 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
264 ; EG: BFE_INT [[RES]]
265 ; EG: BFE_INT [[RES]]
266 ; EG: BFE_INT [[RES]]
267 ; EG: BFE_INT [[RES]]
268 ; EG: LSHR {{\*?}} [[ADDR]]
269 define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
270 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
271 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
272 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
273 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
277 ; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
278 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
279 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
280 ; SI: BUFFER_STORE_DWORDX2
282 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
283 ; EG: BFE_INT [[RES]]
284 ; EG: BFE_INT [[RES]]
285 ; EG: LSHR {{\*?}} [[ADDR]]
286 define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
287 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
288 %shl = shl <2 x i32> %c, <i32 24, i32 24>
289 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
290 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
294 ; FUNC-LABEL: @testcase
295 define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
296 %and_a_1 = and i8 %a, 1
297 %cmp_eq = icmp eq i8 %and_a_1, 0
298 %cmp_slt = icmp slt i8 %a, 0
299 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
300 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
301 %xor = xor i8 %sel0, %sel1
302 store i8 %xor, i8 addrspace(1)* %out
306 ; FUNC-LABEL: @testcase_3
307 define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
308 %and_a_1 = and i8 %a, 1
309 %cmp_eq = icmp eq i8 %and_a_1, 0
310 %cmp_slt = icmp slt i8 %a, 0
311 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
312 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
313 %xor = xor i8 %sel0, %sel1
314 store i8 %xor, i8 addrspace(1)* %out
318 ; FIXME: The BFE should really be eliminated. I think it should happen
319 ; when computeMaskedBitsForTargetNode is implemented for imax.
321 ; FUNC-LABEL: @sext_in_reg_to_illegal_type
322 ; SI: BUFFER_LOAD_SBYTE
325 ; SI: BUFFER_STORE_SHORT
326 define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
327 %tmp5 = load i8 addrspace(1)* %src, align 1
328 %tmp2 = sext i8 %tmp5 to i32
329 %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
330 %tmp4 = trunc i32 %tmp3 to i8
331 %tmp6 = sext i8 %tmp4 to i16
332 store i16 %tmp6, i16 addrspace(1)* %out, align 2