1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone
7 ; FUNC-LABEL: @sext_in_reg_i1_i32
8 ; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
9 ; SI: S_BFE_I32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
10 ; SI: V_MOV_B32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]]
11 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
13 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
14 ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
15 ; EG-NEXT: LSHR * [[ADDR]]
16 define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
17 %shl = shl i32 %in, 31
18 %sext = ashr i32 %shl, 31
19 store i32 %sext, i32 addrspace(1)* %out
23 ; FUNC-LABEL: @sext_in_reg_i8_to_i32
24 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
25 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
26 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
27 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
29 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
31 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
32 ; EG-NEXT: LSHR * [[ADDR]]
33 define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
34 %c = add i32 %a, %b ; add to prevent folding into extload
36 %ashr = ashr i32 %shl, 24
37 store i32 %ashr, i32 addrspace(1)* %out, align 4
41 ; FUNC-LABEL: @sext_in_reg_i16_to_i32
42 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
43 ; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
44 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
45 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
47 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
49 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
50 ; EG-NEXT: LSHR * [[ADDR]]
51 define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
52 %c = add i32 %a, %b ; add to prevent folding into extload
54 %ashr = ashr i32 %shl, 16
55 store i32 %ashr, i32 addrspace(1)* %out, align 4
59 ; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
60 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
61 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
62 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
63 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
65 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
67 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
68 ; EG-NEXT: LSHR * [[ADDR]]
69 define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
70 %c = add <1 x i32> %a, %b ; add to prevent folding into extload
71 %shl = shl <1 x i32> %c, <i32 24>
72 %ashr = ashr <1 x i32> %shl, <i32 24>
73 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
77 ; FUNC-LABEL: @sext_in_reg_i1_to_i64
78 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
79 ; SI: S_BFE_I32 s{{[0-9]+}}, s{{[0-9]+}}, 0x10000
80 ; SI: S_MOV_B32 {{s[0-9]+}}, -1
81 ; SI: BUFFER_STORE_DWORDX2
82 define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
85 %ashr = ashr i64 %shl, 63
86 store i64 %ashr, i64 addrspace(1)* %out, align 8
90 ; FUNC-LABEL: @sext_in_reg_i8_to_i64
91 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
92 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
93 ; SI: S_MOV_B32 {{s[0-9]+}}, -1
94 ; SI: BUFFER_STORE_DWORDX2
96 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
97 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
99 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
100 ; EG: ASHR [[RES_HI]]
104 ;; TODO Check address computation, using | with variables in {{}} does not work,
105 ;; also the _LO/_HI order might be different
106 define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
108 %shl = shl i64 %c, 56
109 %ashr = ashr i64 %shl, 56
110 store i64 %ashr, i64 addrspace(1)* %out, align 8
114 ; FUNC-LABEL: @sext_in_reg_i16_to_i64
115 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
116 ; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
117 ; SI: S_MOV_B32 {{s[0-9]+}}, -1
118 ; SI: BUFFER_STORE_DWORDX2
120 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
121 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
123 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
124 ; EG: ASHR [[RES_HI]]
128 ;; TODO Check address computation, using | with variables in {{}} does not work,
129 ;; also the _LO/_HI order might be different
130 define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
132 %shl = shl i64 %c, 48
133 %ashr = ashr i64 %shl, 48
134 store i64 %ashr, i64 addrspace(1)* %out, align 8
138 ; FUNC-LABEL: @sext_in_reg_i32_to_i64
141 ; SI: S_ADD_I32 [[ADD:s[0-9]+]],
142 ; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31
143 ; SI: BUFFER_STORE_DWORDX2
145 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
146 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
148 ; EG: ADD_INT {{\*?}} [[RES_LO]]
149 ; EG: ASHR [[RES_HI]]
153 ;; TODO Check address computation, using | with variables in {{}} does not work,
154 ;; also the _LO/_HI order might be different
155 define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
157 %shl = shl i64 %c, 32
158 %ashr = ashr i64 %shl, 32
159 store i64 %ashr, i64 addrspace(1)* %out, align 8
163 ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
164 ; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
165 ; XSI: S_BFE_I32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
166 ; XSI: S_ASHR_I32 {{v[0-9]+}}, [[EXTRACT]], 31
167 ; XSI: BUFFER_STORE_DWORD
170 ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
171 ; %c = add <1 x i64> %a, %b
172 ; %shl = shl <1 x i64> %c, <i64 56>
173 ; %ashr = ashr <1 x i64> %shl, <i64 56>
174 ; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
178 ; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
180 ; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
181 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
183 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
188 ; EG: LSHR {{\*?}} [[ADDR]]
189 define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
193 store i32 %y, i32 addrspace(1)* %out
197 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
198 ; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
199 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
200 ; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
201 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
203 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
210 ; EG: LSHR {{\*?}} [[ADDR]]
211 define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
212 %c = add <2 x i32> %a, %b
213 %x = shl <2 x i32> %c, <i32 6, i32 6>
214 %y = ashr <2 x i32> %x, <i32 7, i32 7>
215 store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
220 ; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
221 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
222 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
223 ; SI: BUFFER_STORE_DWORDX2
225 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
226 ; EG: BFE_INT [[RES]]
227 ; EG: BFE_INT [[RES]]
228 ; EG: LSHR {{\*?}} [[ADDR]]
229 define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
230 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
231 %shl = shl <2 x i32> %c, <i32 31, i32 31>
232 %ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
233 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
237 ; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
238 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
239 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
240 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
241 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
242 ; SI: BUFFER_STORE_DWORDX4
244 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
245 ; EG: BFE_INT [[RES]]
246 ; EG: BFE_INT [[RES]]
247 ; EG: BFE_INT [[RES]]
248 ; EG: BFE_INT [[RES]]
249 ; EG: LSHR {{\*?}} [[ADDR]]
250 define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
251 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
252 %shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
253 %ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
254 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
258 ; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
259 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
260 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
261 ; SI: BUFFER_STORE_DWORDX2
263 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
264 ; EG: BFE_INT [[RES]]
265 ; EG: BFE_INT [[RES]]
266 ; EG: LSHR {{\*?}} [[ADDR]]
267 define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
268 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
269 %shl = shl <2 x i32> %c, <i32 24, i32 24>
270 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
271 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
275 ; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
276 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
277 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
278 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
279 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
280 ; SI: BUFFER_STORE_DWORDX4
282 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
283 ; EG: BFE_INT [[RES]]
284 ; EG: BFE_INT [[RES]]
285 ; EG: BFE_INT [[RES]]
286 ; EG: BFE_INT [[RES]]
287 ; EG: LSHR {{\*?}} [[ADDR]]
288 define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
289 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
290 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
291 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
292 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
296 ; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
297 ; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
298 ; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
299 ; SI: BUFFER_STORE_DWORDX2
301 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
302 ; EG: BFE_INT [[RES]]
303 ; EG: BFE_INT [[RES]]
304 ; EG: LSHR {{\*?}} [[ADDR]]
305 define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
306 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
307 %shl = shl <2 x i32> %c, <i32 16, i32 16>
308 %ashr = ashr <2 x i32> %shl, <i32 16, i32 16>
309 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
313 ; FUNC-LABEL: @testcase
314 define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
315 %and_a_1 = and i8 %a, 1
316 %cmp_eq = icmp eq i8 %and_a_1, 0
317 %cmp_slt = icmp slt i8 %a, 0
318 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
319 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
320 %xor = xor i8 %sel0, %sel1
321 store i8 %xor, i8 addrspace(1)* %out
325 ; FUNC-LABEL: @testcase_3
326 define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
327 %and_a_1 = and i8 %a, 1
328 %cmp_eq = icmp eq i8 %and_a_1, 0
329 %cmp_slt = icmp slt i8 %a, 0
330 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
331 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
332 %xor = xor i8 %sel0, %sel1
333 store i8 %xor, i8 addrspace(1)* %out
337 ; FUNC-LABEL: @vgpr_sext_in_reg_v4i8_to_v4i32
338 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
339 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
340 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
341 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
342 define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
343 %loada = load <4 x i32> addrspace(1)* %a, align 16
344 %loadb = load <4 x i32> addrspace(1)* %b, align 16
345 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
346 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
347 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
348 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
352 ; FUNC-LABEL: @vgpr_sext_in_reg_v4i16_to_v4i32
353 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
354 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
355 define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
356 %loada = load <4 x i32> addrspace(1)* %a, align 16
357 %loadb = load <4 x i32> addrspace(1)* %b, align 16
358 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
359 %shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
360 %ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
361 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
365 ; FIXME: The BFE should really be eliminated. I think it should happen
366 ; when computeMaskedBitsForTargetNode is implemented for imax.
368 ; FUNC-LABEL: @sext_in_reg_to_illegal_type
369 ; SI: BUFFER_LOAD_SBYTE
372 ; SI: BUFFER_STORE_SHORT
373 define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
374 %tmp5 = load i8 addrspace(1)* %src, align 1
375 %tmp2 = sext i8 %tmp5 to i32
376 %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
377 %tmp4 = trunc i32 %tmp3 to i8
378 %tmp6 = sext i8 %tmp4 to i16
379 store i16 %tmp6, i16 addrspace(1)* %out, align 2