1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
3 ; TODO: Add RUN and CHECK lines for SI once this test works there
5 @local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
6 @local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
8 ; CHECK: @local_memory_two_objects
10 ; Check that the LDS size emitted correctly
14 ; Make sure the lds writes are using different addresses.
15 ; CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
16 ; CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]]
18 ; GROUP_BARRIER must be the last instruction in a clause
19 ; CHECK: GROUP_BARRIER
20 ; CHECK-NEXT: ALU clause
22 ; Make sure the lds reads are using different addresses.
23 ; CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
24 ; CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
26 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
28 %x.i = call i32 @llvm.r600.read.tidig.x() #0
29 %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
30 store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
31 %mul = shl nsw i32 %x.i, 1
32 %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
33 store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
34 %sub = sub nsw i32 3, %x.i
35 call void @llvm.AMDGPU.barrier.local()
36 %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
37 %0 = load i32 addrspace(3)* %arrayidx2, align 4
38 %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
39 store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
40 %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
41 %1 = load i32 addrspace(3)* %arrayidx4, align 4
42 %add = add nsw i32 %x.i, 4
43 %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
44 store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
48 declare i32 @llvm.r600.read.tidig.x() #0
49 declare void @llvm.AMDGPU.barrier.local()
51 attributes #0 = { readnone }