1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=CHECK %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CHECK %s
4 ; Use a 64-bit value with lo bits that can be represented as an inline constant
5 ; CHECK-LABEL: {{^}}i64_imm_inline_lo:
6 ; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5
7 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
8 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]:
9 define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
11 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
15 ; Use a 64-bit value with hi bits that can be represented as an inline constant
16 ; CHECK-LABEL: {{^}}i64_imm_inline_hi:
17 ; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5
18 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
19 ; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
20 define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
22 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
26 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
27 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
28 ; CHECK: buffer_store_dword [[REG]]
29 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
30 store float 0.0, float addrspace(1)* %out
34 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
35 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
36 ; CHECK: buffer_store_dword [[REG]]
37 define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
38 store float -0.0, float addrspace(1)* %out
42 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
43 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
44 ; CHECK: buffer_store_dword [[REG]]
45 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
46 store float 0.5, float addrspace(1)* %out
50 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
51 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
52 ; CHECK: buffer_store_dword [[REG]]
53 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
54 store float -0.5, float addrspace(1)* %out
58 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
59 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
60 ; CHECK: buffer_store_dword [[REG]]
61 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
62 store float 1.0, float addrspace(1)* %out
66 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
67 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
68 ; CHECK: buffer_store_dword [[REG]]
69 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
70 store float -1.0, float addrspace(1)* %out
74 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
75 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
76 ; CHECK: buffer_store_dword [[REG]]
77 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
78 store float 2.0, float addrspace(1)* %out
82 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
83 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
84 ; CHECK: buffer_store_dword [[REG]]
85 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
86 store float -2.0, float addrspace(1)* %out
90 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
91 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
92 ; CHECK: buffer_store_dword [[REG]]
93 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
94 store float 4.0, float addrspace(1)* %out
98 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
99 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
100 ; CHECK: buffer_store_dword [[REG]]
101 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
102 store float -4.0, float addrspace(1)* %out
106 ; CHECK-LABEL: {{^}}store_literal_imm_f32:
107 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
108 ; CHECK: buffer_store_dword [[REG]]
109 define void @store_literal_imm_f32(float addrspace(1)* %out) {
110 store float 4096.0, float addrspace(1)* %out
114 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
115 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
116 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
117 ; CHECK: buffer_store_dword [[REG]]
118 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
119 %y = fadd float %x, 0.0
120 store float %y, float addrspace(1)* %out
124 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
125 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
126 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
127 ; CHECK: buffer_store_dword [[REG]]
128 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
129 %y = fadd float %x, 0.5
130 store float %y, float addrspace(1)* %out
134 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
135 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
136 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
137 ; CHECK: buffer_store_dword [[REG]]
138 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
139 %y = fadd float %x, -0.5
140 store float %y, float addrspace(1)* %out
144 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
145 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
146 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
147 ; CHECK: buffer_store_dword [[REG]]
148 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
149 %y = fadd float %x, 1.0
150 store float %y, float addrspace(1)* %out
154 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
155 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
156 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
157 ; CHECK: buffer_store_dword [[REG]]
158 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
159 %y = fadd float %x, -1.0
160 store float %y, float addrspace(1)* %out
164 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
165 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
166 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
167 ; CHECK: buffer_store_dword [[REG]]
168 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
169 %y = fadd float %x, 2.0
170 store float %y, float addrspace(1)* %out
174 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
175 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
176 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
177 ; CHECK: buffer_store_dword [[REG]]
178 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
179 %y = fadd float %x, -2.0
180 store float %y, float addrspace(1)* %out
184 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
185 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
186 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
187 ; CHECK: buffer_store_dword [[REG]]
188 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
189 %y = fadd float %x, 4.0
190 store float %y, float addrspace(1)* %out
194 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
195 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
196 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
197 ; CHECK: buffer_store_dword [[REG]]
198 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
199 %y = fadd float %x, -4.0
200 store float %y, float addrspace(1)* %out
204 ; CHECK-LABEL: @commute_add_inline_imm_0.5_f32
205 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
206 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
207 ; CHECK: buffer_store_dword [[REG]]
208 define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
209 %x = load float addrspace(1)* %in
210 %y = fadd float %x, 0.5
211 store float %y, float addrspace(1)* %out
215 ; CHECK-LABEL: @commute_add_literal_f32
216 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
217 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
218 ; CHECK: buffer_store_dword [[REG]]
219 define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
220 %x = load float addrspace(1)* %in
221 %y = fadd float %x, 1024.0
222 store float %y, float addrspace(1)* %out
226 ; CHECK-LABEL: {{^}}add_inline_imm_1_f32
227 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
228 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
229 ; CHECK: buffer_store_dword [[REG]]
230 define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
231 %y = fadd float %x, 0x36a0000000000000
232 store float %y, float addrspace(1)* %out
236 ; CHECK-LABEL: {{^}}add_inline_imm_2_f32
237 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
238 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
239 ; CHECK: buffer_store_dword [[REG]]
240 define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
241 %y = fadd float %x, 0x36b0000000000000
242 store float %y, float addrspace(1)* %out
246 ; CHECK-LABEL: {{^}}add_inline_imm_16_f32
247 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
248 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
249 ; CHECK: buffer_store_dword [[REG]]
250 define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
251 %y = fadd float %x, 0x36e0000000000000
252 store float %y, float addrspace(1)* %out
256 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
257 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
258 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
259 ; CHECK: buffer_store_dword [[REG]]
260 define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
261 %y = fadd float %x, 0xffffffffe0000000
262 store float %y, float addrspace(1)* %out
266 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
267 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
268 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
269 ; CHECK: buffer_store_dword [[REG]]
270 define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
271 %y = fadd float %x, 0xffffffffc0000000
272 store float %y, float addrspace(1)* %out
276 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
277 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
278 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
279 ; CHECK: buffer_store_dword [[REG]]
280 define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
281 %y = fadd float %x, 0xfffffffe00000000
282 store float %y, float addrspace(1)* %out
286 ; CHECK-LABEL: {{^}}add_inline_imm_63_f32
287 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
288 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
289 ; CHECK: buffer_store_dword [[REG]]
290 define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
291 %y = fadd float %x, 0x36ff800000000000
292 store float %y, float addrspace(1)* %out
296 ; CHECK-LABEL: {{^}}add_inline_imm_64_f32
297 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
298 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
299 ; CHECK: buffer_store_dword [[REG]]
300 define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
301 %y = fadd float %x, 0x3700000000000000
302 store float %y, float addrspace(1)* %out
306 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64
307 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
308 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
309 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]]
310 ; CHECK: buffer_store_dwordx2 [[REG]]
311 define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
312 %y = fadd double %x, 0.0
313 store double %y, double addrspace(1)* %out
317 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64
318 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
319 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
320 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]]
321 ; CHECK: buffer_store_dwordx2 [[REG]]
322 define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
323 %y = fadd double %x, 0.5
324 store double %y, double addrspace(1)* %out
328 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64
329 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
330 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
331 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]]
332 ; CHECK: buffer_store_dwordx2 [[REG]]
333 define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
334 %y = fadd double %x, -0.5
335 store double %y, double addrspace(1)* %out
339 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64
340 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
341 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
342 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]]
343 ; CHECK: buffer_store_dwordx2 [[REG]]
344 define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
345 %y = fadd double %x, 1.0
346 store double %y, double addrspace(1)* %out
350 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64
351 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
352 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
353 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]]
354 ; CHECK: buffer_store_dwordx2 [[REG]]
355 define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
356 %y = fadd double %x, -1.0
357 store double %y, double addrspace(1)* %out
361 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64
362 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
363 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
364 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]]
365 ; CHECK: buffer_store_dwordx2 [[REG]]
366 define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
367 %y = fadd double %x, 2.0
368 store double %y, double addrspace(1)* %out
372 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64
373 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
374 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
375 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]]
376 ; CHECK: buffer_store_dwordx2 [[REG]]
377 define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
378 %y = fadd double %x, -2.0
379 store double %y, double addrspace(1)* %out
383 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64
384 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
385 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
386 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]]
387 ; CHECK: buffer_store_dwordx2 [[REG]]
388 define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
389 %y = fadd double %x, 4.0
390 store double %y, double addrspace(1)* %out
394 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64
395 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
396 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
397 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]]
398 ; CHECK: buffer_store_dwordx2 [[REG]]
399 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
400 %y = fadd double %x, -4.0
401 store double %y, double addrspace(1)* %out
406 ; CHECK-LABEL: {{^}}add_inline_imm_1_f64
407 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
408 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
409 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]]
410 ; CHECK: buffer_store_dwordx2 [[REG]]
411 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
412 %y = fadd double %x, 0x0000000000000001
413 store double %y, double addrspace(1)* %out
417 ; CHECK-LABEL: {{^}}add_inline_imm_2_f64
418 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
419 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
420 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]]
421 ; CHECK: buffer_store_dwordx2 [[REG]]
422 define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
423 %y = fadd double %x, 0x0000000000000002
424 store double %y, double addrspace(1)* %out
428 ; CHECK-LABEL: {{^}}add_inline_imm_16_f64
429 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
430 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
431 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]]
432 ; CHECK: buffer_store_dwordx2 [[REG]]
433 define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
434 %y = fadd double %x, 0x0000000000000010
435 store double %y, double addrspace(1)* %out
439 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64
440 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
441 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
442 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]]
443 ; CHECK: buffer_store_dwordx2 [[REG]]
444 define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
445 %y = fadd double %x, 0xffffffffffffffff
446 store double %y, double addrspace(1)* %out
450 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64
451 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
452 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
453 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]]
454 ; CHECK: buffer_store_dwordx2 [[REG]]
455 define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
456 %y = fadd double %x, 0xfffffffffffffffe
457 store double %y, double addrspace(1)* %out
461 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64
462 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
463 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
464 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]]
465 ; CHECK: buffer_store_dwordx2 [[REG]]
466 define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
467 %y = fadd double %x, 0xfffffffffffffff0
468 store double %y, double addrspace(1)* %out
472 ; CHECK-LABEL: {{^}}add_inline_imm_63_f64
473 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
474 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
475 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
476 ; CHECK: buffer_store_dwordx2 [[REG]]
477 define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
478 %y = fadd double %x, 0x000000000000003F
479 store double %y, double addrspace(1)* %out
483 ; CHECK-LABEL: {{^}}add_inline_imm_64_f64
484 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
485 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
486 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]]
487 ; CHECK: buffer_store_dwordx2 [[REG]]
488 define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
489 %y = fadd double %x, 0x0000000000000040
490 store double %y, double addrspace(1)* %out
495 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64
496 ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
497 ; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0
498 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
499 define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
500 store double 0.0, double addrspace(1)* %out