1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3 declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
4 declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
5 declare i32 @llvm.r600.read.tidig.x() #1
6 declare float @llvm.fabs.f32(float) #1
7 declare double @llvm.fabs.f64(double) #1
9 ; SI-LABEL: {{^}}test_isinf_pattern:
10 ; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
11 ; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
14 define void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
15 %fabs = tail call float @llvm.fabs.f32(float %x) #1
16 %cmp = fcmp oeq float %fabs, 0x7FF0000000000000
17 %ext = zext i1 %cmp to i32
18 store i32 %ext, i32 addrspace(1)* %out, align 4
22 ; SI-LABEL: {{^}}test_not_isinf_pattern_0:
25 define void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
26 %fabs = tail call float @llvm.fabs.f32(float %x) #1
27 %cmp = fcmp ueq float %fabs, 0x7FF0000000000000
28 %ext = zext i1 %cmp to i32
29 store i32 %ext, i32 addrspace(1)* %out, align 4
33 ; SI-LABEL: {{^}}test_not_isinf_pattern_1:
36 define void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
37 %fabs = tail call float @llvm.fabs.f32(float %x) #1
38 %cmp = fcmp oeq float %fabs, 0xFFF0000000000000
39 %ext = zext i1 %cmp to i32
40 store i32 %ext, i32 addrspace(1)* %out, align 4
44 attributes #0 = { nounwind }
45 attributes #1 = { nounwind readnone }