1 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.r600.read.tidig.x() #1
6 ; FUNC-LABEL: @test_fmin_legacy_f32
8 ; SI: v_min_legacy_f32_e32
9 define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {
10 %r0 = extractelement <4 x float> %reg0, i32 0
11 %r1 = extractelement <4 x float> %reg0, i32 1
12 %r2 = fcmp uge float %r0, %r1
13 %r3 = select i1 %r2, float %r1, float %r0
14 %vec = insertelement <4 x float> undef, float %r3, i32 0
15 store <4 x float> %vec, <4 x float> addrspace(1)* %out, align 16
19 ; FUNC-LABEL: @test_fmin_legacy_ule_f32
20 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
21 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
22 ; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
23 define void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
24 %tid = call i32 @llvm.r600.read.tidig.x() #1
25 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
26 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
28 %a = load float addrspace(1)* %gep.0, align 4
29 %b = load float addrspace(1)* %gep.1, align 4
31 %cmp = fcmp ule float %a, %b
32 %val = select i1 %cmp, float %a, float %b
33 store float %val, float addrspace(1)* %out, align 4
37 ; FUNC-LABEL: @test_fmin_legacy_ole_f32
38 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
39 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
40 ; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
41 define void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
42 %tid = call i32 @llvm.r600.read.tidig.x() #1
43 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
44 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
46 %a = load float addrspace(1)* %gep.0, align 4
47 %b = load float addrspace(1)* %gep.1, align 4
49 %cmp = fcmp ole float %a, %b
50 %val = select i1 %cmp, float %a, float %b
51 store float %val, float addrspace(1)* %out, align 4
55 ; FUNC-LABEL: @test_fmin_legacy_olt_f32
56 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
57 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
58 ; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
59 define void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
60 %tid = call i32 @llvm.r600.read.tidig.x() #1
61 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
62 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
64 %a = load float addrspace(1)* %gep.0, align 4
65 %b = load float addrspace(1)* %gep.1, align 4
67 %cmp = fcmp olt float %a, %b
68 %val = select i1 %cmp, float %a, float %b
69 store float %val, float addrspace(1)* %out, align 4
73 ; FUNC-LABEL: @test_fmin_legacy_ult_f32
74 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
75 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
76 ; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
77 define void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
78 %tid = call i32 @llvm.r600.read.tidig.x() #1
79 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
80 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
82 %a = load float addrspace(1)* %gep.0, align 4
83 %b = load float addrspace(1)* %gep.1, align 4
85 %cmp = fcmp ult float %a, %b
86 %val = select i1 %cmp, float %a, float %b
87 store float %val, float addrspace(1)* %out, align 4
91 ; FUNC-LABEL: @test_fmin_legacy_ole_f32_multi_use
92 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
93 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
96 ; SI-NEXT: v_cndmask_b32
99 define void @test_fmin_legacy_ole_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
100 %tid = call i32 @llvm.r600.read.tidig.x() #1
101 %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
102 %gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
104 %a = load float addrspace(1)* %gep.0, align 4
105 %b = load float addrspace(1)* %gep.1, align 4
107 %cmp = fcmp ole float %a, %b
108 %val0 = select i1 %cmp, float %a, float %b
109 store float %val0, float addrspace(1)* %out0, align 4
110 store i1 %cmp, i1 addrspace(1)* %out1
114 attributes #0 = { nounwind }
115 attributes #1 = { nounwind readnone }