1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3 declare float @llvm.maxnum.f32(float, float) nounwind readnone
5 ; SI-LABEL: {{^}}test_fmax3_olt_0:
6 ; SI: buffer_load_dword [[REGA:v[0-9]+]]
7 ; SI: buffer_load_dword [[REGB:v[0-9]+]]
8 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
9 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
10 ; SI: buffer_store_dword [[RESULT]],
12 define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
13 %a = load float addrspace(1)* %aptr, align 4
14 %b = load float addrspace(1)* %bptr, align 4
15 %c = load float addrspace(1)* %cptr, align 4
16 %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
17 %f1 = call float @llvm.maxnum.f32(float %f0, float %c) nounwind readnone
18 store float %f1, float addrspace(1)* %out, align 4
22 ; Commute operand of second fmax
23 ; SI-LABEL: {{^}}test_fmax3_olt_1:
24 ; SI: buffer_load_dword [[REGA:v[0-9]+]]
25 ; SI: buffer_load_dword [[REGB:v[0-9]+]]
26 ; SI: buffer_load_dword [[REGC:v[0-9]+]]
27 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
28 ; SI: buffer_store_dword [[RESULT]],
30 define void @test_fmax3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
31 %a = load float addrspace(1)* %aptr, align 4
32 %b = load float addrspace(1)* %bptr, align 4
33 %c = load float addrspace(1)* %cptr, align 4
34 %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
35 %f1 = call float @llvm.maxnum.f32(float %c, float %f0) nounwind readnone
36 store float %f1, float addrspace(1)* %out, align 4