1 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s
3 define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
6 %tmp = load <16 x i8>* %A
7 %tmp2 = load <16 x i8>* %B
8 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
10 store <16 x i8> %tmp3, <16 x i8>* %A
14 define void @VPKUHUM_xx(<16 x i8>* %A) {
17 %tmp = load <16 x i8>* %A
18 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
20 store <16 x i8> %tmp2, <16 x i8>* %A
24 define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
27 %tmp = load <16 x i8>* %A
28 %tmp2 = load <16 x i8>* %B
29 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
31 store <16 x i8> %tmp3, <16 x i8>* %A
35 define void @VPKUWUM_xx(<16 x i8>* %A) {
38 %tmp = load <16 x i8>* %A
39 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
41 store <16 x i8> %tmp2, <16 x i8>* %A
45 define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
48 %tmp = load <16 x i8>* %A
49 %tmp2 = load <16 x i8>* %B
50 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
51 ; CHECK: lvx [[REG1:[0-9]+]]
52 ; CHECK: lvx [[REG2:[0-9]+]]
53 ; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
54 store <16 x i8> %tmp3, <16 x i8>* %A
58 define void @VMRGLB_xx(<16 x i8>* %A) {
61 %tmp = load <16 x i8>* %A
62 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
64 store <16 x i8> %tmp2, <16 x i8>* %A
68 define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
71 %tmp = load <16 x i8>* %A
72 %tmp2 = load <16 x i8>* %B
73 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
74 ; CHECK: lvx [[REG1:[0-9]+]]
75 ; CHECK: lvx [[REG2:[0-9]+]]
76 ; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
77 store <16 x i8> %tmp3, <16 x i8>* %A
81 define void @VMRGHB_xx(<16 x i8>* %A) {
84 %tmp = load <16 x i8>* %A
85 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
87 store <16 x i8> %tmp2, <16 x i8>* %A
91 define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
94 %tmp = load <16 x i8>* %A
95 %tmp2 = load <16 x i8>* %B
96 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
97 ; CHECK: lvx [[REG1:[0-9]+]]
98 ; CHECK: lvx [[REG2:[0-9]+]]
99 ; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
100 store <16 x i8> %tmp3, <16 x i8>* %A
104 define void @VMRGLH_xx(<16 x i8>* %A) {
107 %tmp = load <16 x i8>* %A
108 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
110 store <16 x i8> %tmp2, <16 x i8>* %A
114 define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
117 %tmp = load <16 x i8>* %A
118 %tmp2 = load <16 x i8>* %B
119 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
120 ; CHECK: lvx [[REG1:[0-9]+]]
121 ; CHECK: lvx [[REG2:[0-9]+]]
122 ; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
123 store <16 x i8> %tmp3, <16 x i8>* %A
127 define void @VMRGHH_xx(<16 x i8>* %A) {
130 %tmp = load <16 x i8>* %A
131 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
133 store <16 x i8> %tmp2, <16 x i8>* %A
137 define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
140 %tmp = load <16 x i8>* %A
141 %tmp2 = load <16 x i8>* %B
142 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
143 ; CHECK: lvx [[REG1:[0-9]+]]
144 ; CHECK: lvx [[REG2:[0-9]+]]
145 ; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
146 store <16 x i8> %tmp3, <16 x i8>* %A
150 define void @VMRGLW_xx(<16 x i8>* %A) {
153 %tmp = load <16 x i8>* %A
154 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
156 store <16 x i8> %tmp2, <16 x i8>* %A
160 define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
163 %tmp = load <16 x i8>* %A
164 %tmp2 = load <16 x i8>* %B
165 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
166 ; CHECK: lvx [[REG1:[0-9]+]]
167 ; CHECK: lvx [[REG2:[0-9]+]]
168 ; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
169 store <16 x i8> %tmp3, <16 x i8>* %A
173 define void @VMRGHW_xx(<16 x i8>* %A) {
176 %tmp = load <16 x i8>* %A
177 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
179 store <16 x i8> %tmp2, <16 x i8>* %A
183 define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
186 %tmp = load <16 x i8>* %A
187 %tmp2 = load <16 x i8>* %B
188 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
190 store <16 x i8> %tmp3, <16 x i8>* %A
194 define void @VSLDOI_xx(<16 x i8>* %A) {
197 %tmp = load <16 x i8>* %A
198 %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4>
200 store <16 x i8> %tmp2, <16 x i8>* %A