1 ; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s
2 ; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s
4 ; Test correct assembly code generation for thread-local storage using
5 ; the local dynamic model.
7 @a = hidden thread_local global i32 0, align 4
9 define signext i32 @main() nounwind {
11 %retval = alloca i32, align 4
12 store i32 0, i32* %retval
13 %0 = load i32* @a, align 4
18 ; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
19 ; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l
20 ; OPT0: bl __tls_get_addr(a@tlsld)
22 ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
23 ; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
25 ; Test peephole optimization for thread-local storage using the
26 ; local dynamic model.
29 ; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
30 ; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l
31 ; OPT1: bl __tls_get_addr(a@tlsld)
33 ; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
34 ; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
36 ; Test correct assembly code generation for thread-local storage using
37 ; the general dynamic model.
39 @a2 = thread_local global i32 0, align 4
41 define signext i32 @main2() nounwind {
43 %retval = alloca i32, align 4
44 store i32 0, i32* %retval
45 %0 = load i32* @a2, align 4
50 ; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
51 ; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l
52 ; OPT1: bl __tls_get_addr(a2@tlsgd)