1 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
2 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
5 ; Note: Lots of tests use inline asm instead of regular calls.
6 ; This allows to have a better control on what the allocation will do.
7 ; Otherwise, we may have spill right in the entry block, defeating
8 ; shrink-wrapping. Moreover, some of the inline asm statement (nop)
9 ; are here to ensure that the related paths do not end up as critical
13 ; Initial motivating example: Simple diamond with a call just on one side.
16 ; Compare the arguments and return
18 ; ENABLE: cmpw 0, 3, 4
19 ; ENABLE-NEXT: bgelr 0
22 ; At a minimum, we save/restore the link register. Other registers may be saved
26 ; Compare the arguments and jump to exit.
27 ; After the prologue is set.
28 ; DISABLE: cmpw 0, 3, 4
29 ; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
31 ; Store %a on the stack
32 ; CHECK: stw 3, {{[0-9]+([0-9]+)}}
33 ; Set the alloca address in the second argument.
34 ; CHECK-NEXT: addi 4, 1, {{[0-9]+}}
35 ; Set the first argument to zero.
37 ; CHECK-NEXT: bl doSomething
39 ; With shrink-wrapping, epilogue is just after the call.
40 ; Restore the link register and return.
41 ; Note that there could be other epilog code before the link register is
42 ; restored but we will not check for it here.
46 ; DISABLE: [[EXIT_LABEL]]:
48 ; Without shrink-wrapping, epilogue is in the exit block.
49 ; Epilogue code. (What we pop does not matter.)
54 define i32 @foo(i32 %a, i32 %b) {
55 %tmp = alloca i32, align 4
56 %tmp2 = icmp slt i32 %a, %b
57 br i1 %tmp2, label %true, label %false
60 store i32 %a, i32* %tmp, align 4
61 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
65 %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
69 ; Function Attrs: optsize
70 declare i32 @doSomething(i32, i32*)
74 ; Check that we do not perform the restore inside the loop whereas the save
76 ; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
78 ; Shrink-wrapping allows to skip the prologue in the else case.
79 ; ENABLE: cmplwi 0, 3, 0
80 ; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
83 ; Make sure we save the link register
86 ; DISABLE: cmplwi 0, 3, 0
87 ; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
90 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
91 ; CHECK-DAG: li [[IV:[0-9]+]], 10
94 ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
96 ; CHECK-DAG: addi [[IV]], [[IV]], -1
97 ; CHECK-DAG: add [[SUM]], 3, [[SUM]]
98 ; CHECK-NEXT: cmplwi [[IV]], 0
99 ; CHECK-NEXT: bne 0, .[[LOOP]]
102 ; CHECK: slwi 3, [[SUM]], 3
105 ; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
107 ; DISABLE: .[[ELSE_LABEL]]: # %if.else
108 ; Shift second argument by one and store into returned register.
109 ; DISABLE: slwi 3, 4, 1
110 ; DISABLE: .[[EPILOG_BB]]: # %if.end
116 ; ENABLE: .[[ELSE_LABEL]]: # %if.else
117 ; Shift second argument by one and store into returned register.
118 ; ENABLE: slwi 3, 4, 1
120 define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
122 %tobool = icmp eq i32 %cond, 0
123 br i1 %tobool, label %if.else, label %for.preheader
126 tail call void asm "nop", ""()
129 for.body: ; preds = %entry, %for.body
130 %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
131 %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
132 %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
133 %add = add nsw i32 %call, %sum.04
134 %inc = add nuw nsw i32 %i.05, 1
135 %exitcond = icmp eq i32 %inc, 10
136 br i1 %exitcond, label %for.end, label %for.body
138 for.end: ; preds = %for.body
139 %shl = shl i32 %add, 3
142 if.else: ; preds = %entry
143 %mul = shl nsw i32 %N, 1
146 if.end: ; preds = %if.else, %for.end
147 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
151 declare i32 @something(...)
153 ; Check that we do not perform the shrink-wrapping inside the loop even
154 ; though that would be legal. The cost model must prevent that.
155 ; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
157 ; Make sure we save the link register before the call
161 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
162 ; CHECK-DAG: li [[IV:[0-9]+]], 10
165 ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
166 ; CHECK: bl something
167 ; CHECK-DAG: addi [[IV]], [[IV]], -1
168 ; CHECK-DAG: add [[SUM]], 3, [[SUM]]
169 ; CHECK-NEXT: cmplwi [[IV]], 0
170 ; CHECK-NEXT: bne 0, .[[LOOP]]
176 define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
178 br label %for.preheader
181 tail call void asm "nop", ""()
184 for.body: ; preds = %for.body, %entry
185 %i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
186 %sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
187 %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
188 %add = add nsw i32 %call, %sum.03
189 %inc = add nuw nsw i32 %i.04, 1
190 %exitcond = icmp eq i32 %inc, 10
191 br i1 %exitcond, label %for.exit, label %for.body
194 tail call void asm "nop", ""()
197 for.end: ; preds = %for.body
202 ; Check with a more complex case that we do not have save within the loop and
204 ; CHECK-LABEL: loopInfoSaveOutsideLoop:
206 ; ENABLE: cmplwi 0, 3, 0
207 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
210 ; Make sure we save the link register
213 ; DISABLE: cmplwi 0, 3, 0
214 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
217 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
218 ; CHECK-DAG: li [[IV:[0-9]+]], 10
221 ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
222 ; CHECK: bl something
223 ; CHECK-DAG: addi [[IV]], [[IV]], -1
224 ; CHECK-DAG: add [[SUM]], 3, [[SUM]]
225 ; CHECK-NEXT: cmplwi [[IV]], 0
226 ; CHECK-NEXT: bne 0, .[[LOOP]]
229 ; CHECK: bl somethingElse
230 ; CHECK: slwi 3, [[SUM]], 3
233 ; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
235 ; DISABLE: .[[ELSE_LABEL]]: # %if.else
236 ; Shift second argument by one and store into returned register.
237 ; DISABLE: slwi 3, 4, 1
239 ; DISABLE: .[[EPILOG_BB]]: # %if.end
244 ; ENABLE: .[[ELSE_LABEL]]: # %if.else
245 ; Shift second argument by one and store into returned register.
246 ; ENABLE: slwi 3, 4, 1
248 define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
250 %tobool = icmp eq i32 %cond, 0
251 br i1 %tobool, label %if.else, label %for.preheader
254 tail call void asm "nop", ""()
257 for.body: ; preds = %entry, %for.body
258 %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
259 %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
260 %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
261 %add = add nsw i32 %call, %sum.04
262 %inc = add nuw nsw i32 %i.05, 1
263 %exitcond = icmp eq i32 %inc, 10
264 br i1 %exitcond, label %for.end, label %for.body
266 for.end: ; preds = %for.body
267 tail call void bitcast (void (...)* @somethingElse to void ()*)()
268 %shl = shl i32 %add, 3
271 if.else: ; preds = %entry
272 %mul = shl nsw i32 %N, 1
275 if.end: ; preds = %if.else, %for.end
276 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
280 declare void @somethingElse(...)
282 ; Check with a more complex case that we do not have restore within the loop and
284 ; CHECK-LABEL: loopInfoRestoreOutsideLoop:
286 ; ENABLE: cmplwi 0, 3, 0
287 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
290 ; Make sure we save the link register
293 ; DISABLE: cmplwi 0, 3, 0
294 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
296 ; CHECK: bl somethingElse
299 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
300 ; CHECK-DAG: li [[IV:[0-9]+]], 10
303 ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
304 ; CHECK: bl something
305 ; CHECK-DAG: addi [[IV]], [[IV]], -1
306 ; CHECK-DAG: add [[SUM]], 3, [[SUM]]
307 ; CHECK-NEXT: cmplwi [[IV]], 0
308 ; CHECK-NEXT: bne 0, .[[LOOP]]
313 ; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
315 ; DISABLE: .[[ELSE_LABEL]]: # %if.else
316 ; Shift second argument by one and store into returned register.
317 ; DISABLE: slwi 3, 4, 1
318 ; DISABLE: .[[EPILOG_BB]]: # %if.end
324 ; ENABLE: .[[ELSE_LABEL]]: # %if.else
325 ; Shift second argument by one and store into returned register.
326 ; ENABLE: slwi 3, 4, 1
328 define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
330 %tobool = icmp eq i32 %cond, 0
331 br i1 %tobool, label %if.else, label %if.then
333 if.then: ; preds = %entry
334 tail call void bitcast (void (...)* @somethingElse to void ()*)()
337 for.body: ; preds = %for.body, %if.then
338 %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
339 %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
340 %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
341 %add = add nsw i32 %call, %sum.04
342 %inc = add nuw nsw i32 %i.05, 1
343 %exitcond = icmp eq i32 %inc, 10
344 br i1 %exitcond, label %for.end, label %for.body
346 for.end: ; preds = %for.body
347 %shl = shl i32 %add, 3
350 if.else: ; preds = %entry
351 %mul = shl nsw i32 %N, 1
354 if.end: ; preds = %if.else, %for.end
355 %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
359 ; Check that we handle function with no frame information correctly.
360 ; CHECK-LABEL: emptyFrame:
362 ; CHECK-NEXT: li 3, 0
364 define i32 @emptyFrame() {
370 ; Check that we handle inline asm correctly.
371 ; CHECK-LABEL: inlineAsm:
373 ; ENABLE: cmplwi 0, 3, 0
374 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
377 ; Make sure we save the CSR used in the inline asm: r14
378 ; ENABLE-DAG: li [[IV:[0-9]+]], 10
379 ; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
381 ; DISABLE: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
382 ; DISABLE: cmplwi 0, 3, 0
383 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
384 ; DISABLE: li [[IV:[0-9]+]], 10
387 ; CHECK: mtctr [[IV]]
389 ; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body
390 ; Inline asm statement.
391 ; CHECK: addi 14, 14, 1
392 ; CHECK: bdnz .[[LOOP_LABEL]]
396 ; CHECK-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
400 ; CHECK: [[ELSE_LABEL]]
401 ; CHECK-NEXT: slwi 3, 4, 1
402 ; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
405 define i32 @inlineAsm(i32 %cond, i32 %N) {
407 %tobool = icmp eq i32 %cond, 0
408 br i1 %tobool, label %if.else, label %for.preheader
411 tail call void asm "nop", ""()
414 for.body: ; preds = %entry, %for.body
415 %i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
416 tail call void asm "addi 14, 14, 1", "~{r14}"()
417 %inc = add nuw nsw i32 %i.03, 1
418 %exitcond = icmp eq i32 %inc, 10
419 br i1 %exitcond, label %for.exit, label %for.body
422 tail call void asm "nop", ""()
425 if.else: ; preds = %entry
426 %mul = shl nsw i32 %N, 1
429 if.end: ; preds = %for.body, %if.else
430 %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
435 ; Check that we handle calls to variadic functions correctly.
436 ; CHECK-LABEL: callVariadicFunc:
438 ; ENABLE: cmplwi 0, 3, 0
439 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
444 ; DISABLE: cmplwi 0, 3, 0
445 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
447 ; Setup of the varags.
449 ; CHECK-NEXT: mr 5, 3
450 ; CHECK-NEXT: mr 6, 3
451 ; CHECK-NEXT: mr 7, 3
452 ; CHECK-NEXT: mr 8, 3
453 ; CHECK-NEXT: mr 9, 3
454 ; CHECK-NEXT: bl someVariadicFunc
455 ; CHECK: slwi 3, 3, 3
456 ; DISABLE: b .[[EPILOGUE_BB:LBB[0-9_]+]]
461 ; CHECK: .[[ELSE_LABEL]]: # %if.else
462 ; CHECK-NEXT: slwi 3, 4, 1
464 ; DISABLE: .[[EPILOGUE_BB]]: # %if.end
467 define i32 @callVariadicFunc(i32 %cond, i32 %N) {
469 %tobool = icmp eq i32 %cond, 0
470 br i1 %tobool, label %if.else, label %if.then
472 if.then: ; preds = %entry
473 %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
474 %shl = shl i32 %call, 3
477 if.else: ; preds = %entry
478 %mul = shl nsw i32 %N, 1
481 if.end: ; preds = %if.else, %if.then
482 %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
486 declare i32 @someVariadicFunc(i32, ...)
490 ; Make sure we do not insert unreachable code after noreturn function.
491 ; Although this is not incorrect to insert such code, it is useless
492 ; and it hurts the binary size.
494 ; CHECK-LABEL: noreturn:
498 ; CHECK-NEXT: bne 0, .[[ABORT:LBB[0-9_]+]]
506 ; CHECK: .[[ABORT]]: # %if.abort
512 define i32 @noreturn(i8 signext %bad_thing) {
514 %tobool = icmp eq i8 %bad_thing, 0
515 br i1 %tobool, label %if.end, label %if.abort
518 tail call void @abort() #0
525 declare void @abort() #0
527 attributes #0 = { noreturn nounwind }
530 ; Make sure that we handle infinite loops properly When checking that the Save
531 ; and Restore blocks are control flow equivalent, the loop searches for the
532 ; immediate (post) dominator for the (restore) save blocks. When either the Save
533 ; or Restore block is located in an infinite loop the only immediate (post)
534 ; dominator is itself. In this case, we cannot perform shrink wrapping, but we
535 ; should return gracefully and continue compilation.
536 ; The only condition for this test is the compilation finishes correctly.
538 ; CHECK-LABEL: infiniteloop
540 define void @infiniteloop() {
542 br i1 undef, label %if.then, label %if.end
545 %ptr = alloca i32, i32 4
548 for.body: ; preds = %for.body, %entry
549 %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
550 %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
551 %add = add nsw i32 %call, %sum.03
552 store i32 %add, i32* %ptr
559 ; Another infinite loop test this time with a body bigger than just one block.
560 ; CHECK-LABEL: infiniteloop2
562 define void @infiniteloop2() {
564 br i1 undef, label %if.then, label %if.end
567 %ptr = alloca i32, i32 4
570 for.body: ; preds = %for.body, %entry
571 %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]
572 %call = tail call i32 asm "mftb $0, 268", "=r,~{r14}"()
573 %add = add nsw i32 %call, %sum.03
574 store i32 %add, i32* %ptr
575 br i1 undef, label %body1, label %body2
578 tail call void asm sideeffect "nop", "~{r14}"()
582 tail call void asm sideeffect "nop", "~{r14}"()
589 ; Another infinite loop test this time with two nested infinite loop.
590 ; CHECK-LABEL: infiniteloop3
592 define void @infiniteloop3() {
594 br i1 undef, label %loop2a, label %body
596 body: ; preds = %entry
597 br i1 undef, label %loop2a, label %end
599 loop1: ; preds = %loop2a, %loop2b
600 %var.phi = phi i32* [ %next.phi, %loop2b ], [ %var, %loop2a ]
601 %next.phi = phi i32* [ %next.load, %loop2b ], [ %next.var, %loop2a ]
602 %0 = icmp eq i32* %var, null
603 %next.load = load i32*, i32** undef
604 br i1 %0, label %loop2a, label %loop2b
606 loop2a: ; preds = %loop1, %body, %entry
607 %var = phi i32* [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ]
608 %next.var = phi i32* [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ]
611 loop2b: ; preds = %loop1
612 %gep1 = bitcast i32* %var.phi to i32*
613 %next.ptr = bitcast i32* %gep1 to i32**
614 store i32* %next.phi, i32** %next.ptr
621 @columns = external global [0 x i32], align 4
622 @lock = common global i32 0, align 4
623 @htindex = common global i32 0, align 4
624 @stride = common global i32 0, align 4
625 @ht = common global i32* null, align 8
626 @he = common global i8* null, align 8
628 ; Test for a bug that was caused when save point was equal to restore point.
629 ; Function Attrs: nounwind
630 ; CHECK-LABEL: transpose
632 ; Store of callee-save register saved by shrink wrapping
633 ; CHECK: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
635 ; Reload of callee-save register
636 ; CHECK: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
638 ; Ensure no subsequent uses of callee-save register before end of function
639 ; CHECK-NOT: {{[a-z]+}} [[CSR]]
641 define signext i32 @transpose() {
643 %0 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 1), align 4
644 %shl.i = shl i32 %0, 7
645 %1 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 2), align 4
646 %or.i = or i32 %shl.i, %1
647 %shl1.i = shl i32 %or.i, 7
648 %2 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 3), align 4
649 %or2.i = or i32 %shl1.i, %2
650 %3 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 7), align 4
651 %shl3.i = shl i32 %3, 7
652 %4 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 6), align 4
653 %or4.i = or i32 %shl3.i, %4
654 %shl5.i = shl i32 %or4.i, 7
655 %5 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 5), align 4
656 %or6.i = or i32 %shl5.i, %5
657 %cmp.i = icmp ugt i32 %or2.i, %or6.i
658 br i1 %cmp.i, label %cond.true.i, label %cond.false.i
661 %shl7.i = shl i32 %or2.i, 7
662 %6 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 4), align 4
663 %or8.i = or i32 %6, %shl7.i
664 %conv.i = zext i32 %or8.i to i64
665 %shl9.i = shl nuw nsw i64 %conv.i, 21
666 %conv10.i = zext i32 %or6.i to i64
667 %or11.i = or i64 %shl9.i, %conv10.i
671 %shl12.i = shl i32 %or6.i, 7
672 %7 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 4), align 4
673 %or13.i = or i32 %7, %shl12.i
674 %conv14.i = zext i32 %or13.i to i64
675 %shl15.i = shl nuw nsw i64 %conv14.i, 21
676 %conv16.i = zext i32 %or2.i to i64
677 %or17.i = or i64 %shl15.i, %conv16.i
681 %cond.i = phi i64 [ %or11.i, %cond.true.i ], [ %or17.i, %cond.false.i ]
682 %shr.29.i = lshr i64 %cond.i, 17
683 %conv18.i = trunc i64 %shr.29.i to i32
684 store i32 %conv18.i, i32* @lock, align 4
685 %rem.i = srem i64 %cond.i, 1050011
686 %conv19.i = trunc i64 %rem.i to i32
687 store i32 %conv19.i, i32* @htindex, align 4
688 %rem20.i = urem i32 %conv18.i, 179
689 %add.i = or i32 %rem20.i, 131072
690 store i32 %add.i, i32* @stride, align 4
691 %8 = load i32*, i32** @ht, align 8
692 %arrayidx = getelementptr inbounds i32, i32* %8, i64 %rem.i
693 %9 = load i32, i32* %arrayidx, align 4
694 %cmp1 = icmp eq i32 %9, %conv18.i
695 br i1 %cmp1, label %if.then, label %if.end
698 %idxprom.lcssa = phi i64 [ %rem.i, %hash.exit ], [ %idxprom.1, %if.end ], [ %idxprom.2, %if.end.1 ], [ %idxprom.3, %if.end.2 ], [ %idxprom.4, %if.end.3 ], [ %idxprom.5, %if.end.4 ], [ %idxprom.6, %if.end.5 ], [ %idxprom.7, %if.end.6 ]
699 %10 = load i8*, i8** @he, align 8
700 %arrayidx3 = getelementptr inbounds i8, i8* %10, i64 %idxprom.lcssa
701 %11 = load i8, i8* %arrayidx3, align 1
702 %conv = sext i8 %11 to i32
706 %add = add nsw i32 %add.i, %conv19.i
707 %cmp4 = icmp sgt i32 %add, 1050010
708 %sub = add nsw i32 %add, -1050011
709 %sub.add = select i1 %cmp4, i32 %sub, i32 %add
710 %idxprom.1 = sext i32 %sub.add to i64
711 %arrayidx.1 = getelementptr inbounds i32, i32* %8, i64 %idxprom.1
712 %12 = load i32, i32* %arrayidx.1, align 4
713 %cmp1.1 = icmp eq i32 %12, %conv18.i
714 br i1 %cmp1.1, label %if.then, label %if.end.1
717 %retval.0 = phi i32 [ %conv, %if.then ], [ -128, %if.end.6 ]
721 %add.1 = add nsw i32 %add.i, %sub.add
722 %cmp4.1 = icmp sgt i32 %add.1, 1050010
723 %sub.1 = add nsw i32 %add.1, -1050011
724 %sub.add.1 = select i1 %cmp4.1, i32 %sub.1, i32 %add.1
725 %idxprom.2 = sext i32 %sub.add.1 to i64
726 %arrayidx.2 = getelementptr inbounds i32, i32* %8, i64 %idxprom.2
727 %13 = load i32, i32* %arrayidx.2, align 4
728 %cmp1.2 = icmp eq i32 %13, %conv18.i
729 br i1 %cmp1.2, label %if.then, label %if.end.2
732 %add.2 = add nsw i32 %add.i, %sub.add.1
733 %cmp4.2 = icmp sgt i32 %add.2, 1050010
734 %sub.2 = add nsw i32 %add.2, -1050011
735 %sub.add.2 = select i1 %cmp4.2, i32 %sub.2, i32 %add.2
736 %idxprom.3 = sext i32 %sub.add.2 to i64
737 %arrayidx.3 = getelementptr inbounds i32, i32* %8, i64 %idxprom.3
738 %14 = load i32, i32* %arrayidx.3, align 4
739 %cmp1.3 = icmp eq i32 %14, %conv18.i
740 br i1 %cmp1.3, label %if.then, label %if.end.3
743 %add.3 = add nsw i32 %add.i, %sub.add.2
744 %cmp4.3 = icmp sgt i32 %add.3, 1050010
745 %sub.3 = add nsw i32 %add.3, -1050011
746 %sub.add.3 = select i1 %cmp4.3, i32 %sub.3, i32 %add.3
747 %idxprom.4 = sext i32 %sub.add.3 to i64
748 %arrayidx.4 = getelementptr inbounds i32, i32* %8, i64 %idxprom.4
749 %15 = load i32, i32* %arrayidx.4, align 4
750 %cmp1.4 = icmp eq i32 %15, %conv18.i
751 br i1 %cmp1.4, label %if.then, label %if.end.4
754 %add.4 = add nsw i32 %add.i, %sub.add.3
755 %cmp4.4 = icmp sgt i32 %add.4, 1050010
756 %sub.4 = add nsw i32 %add.4, -1050011
757 %sub.add.4 = select i1 %cmp4.4, i32 %sub.4, i32 %add.4
758 %idxprom.5 = sext i32 %sub.add.4 to i64
759 %arrayidx.5 = getelementptr inbounds i32, i32* %8, i64 %idxprom.5
760 %16 = load i32, i32* %arrayidx.5, align 4
761 %cmp1.5 = icmp eq i32 %16, %conv18.i
762 br i1 %cmp1.5, label %if.then, label %if.end.5
765 %add.5 = add nsw i32 %add.i, %sub.add.4
766 %cmp4.5 = icmp sgt i32 %add.5, 1050010
767 %sub.5 = add nsw i32 %add.5, -1050011
768 %sub.add.5 = select i1 %cmp4.5, i32 %sub.5, i32 %add.5
769 %idxprom.6 = sext i32 %sub.add.5 to i64
770 %arrayidx.6 = getelementptr inbounds i32, i32* %8, i64 %idxprom.6
771 %17 = load i32, i32* %arrayidx.6, align 4
772 %cmp1.6 = icmp eq i32 %17, %conv18.i
773 br i1 %cmp1.6, label %if.then, label %if.end.6
776 %add.6 = add nsw i32 %add.i, %sub.add.5
777 %cmp4.6 = icmp sgt i32 %add.6, 1050010
778 %sub.6 = add nsw i32 %add.6, -1050011
779 %sub.add.6 = select i1 %cmp4.6, i32 %sub.6, i32 %add.6
780 %idxprom.7 = sext i32 %sub.add.6 to i64
781 %arrayidx.7 = getelementptr inbounds i32, i32* %8, i64 %idxprom.7
782 %18 = load i32, i32* %arrayidx.7, align 4
783 %cmp1.7 = icmp eq i32 %18, %conv18.i
784 br i1 %cmp1.7, label %if.then, label %cleanup