1 ; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
2 ; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
5 ; All test functions do the same thing - they return the first variable
8 ; All CHECK's do the same thing - they check whether variable arguments from
9 ; registers are placed on correct stack locations, and whether the first
10 ; variable argument is returned from the correct stack location.
13 declare void @llvm.va_start(i8*) nounwind
14 declare void @llvm.va_end(i8*) nounwind
17 define i32 @va1(i32 %a, ...) nounwind {
19 %a.addr = alloca i32, align 4
20 %ap = alloca i8*, align 4
21 %b = alloca i32, align 4
22 store i32 %a, i32* %a.addr, align 4
23 %ap1 = bitcast i8** %ap to i8*
24 call void @llvm.va_start(i8* %ap1)
25 %0 = va_arg i8** %ap, i32
26 store i32 %0, i32* %b, align 4
27 %ap2 = bitcast i8** %ap to i8*
28 call void @llvm.va_end(i8* %ap2)
29 %tmp = load i32* %b, align 4
33 ; CHECK: addiu $sp, $sp, -32
34 ; CHECK: sw $5, 36($sp)
35 ; CHECK: sw $6, 40($sp)
36 ; CHECK: sw $7, 44($sp)
37 ; CHECK: lw $2, 36($sp)
40 ; check whether the variable double argument will be accessed from the 8-byte
41 ; aligned location (i.e. whether the address is computed by adding 7 and
42 ; clearing lower 3 bits)
43 define double @va2(i32 %a, ...) nounwind {
45 %a.addr = alloca i32, align 4
46 %ap = alloca i8*, align 4
47 %b = alloca double, align 8
48 store i32 %a, i32* %a.addr, align 4
49 %ap1 = bitcast i8** %ap to i8*
50 call void @llvm.va_start(i8* %ap1)
51 %0 = va_arg i8** %ap, double
52 store double %0, double* %b, align 8
53 %ap2 = bitcast i8** %ap to i8*
54 call void @llvm.va_end(i8* %ap2)
55 %tmp = load double* %b, align 8
59 ; CHECK: addiu $sp, $sp, -40
60 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
61 ; CHECK: sw $5, 44($sp)
62 ; CHECK: sw $6, 48($sp)
63 ; CHECK: sw $7, 52($sp)
64 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
65 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
66 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
67 ; CHECK: ldc1 $f0, 0($[[R3]])
71 define i32 @va3(double %a, ...) nounwind {
73 %a.addr = alloca double, align 8
74 %ap = alloca i8*, align 4
75 %b = alloca i32, align 4
76 store double %a, double* %a.addr, align 8
77 %ap1 = bitcast i8** %ap to i8*
78 call void @llvm.va_start(i8* %ap1)
79 %0 = va_arg i8** %ap, i32
80 store i32 %0, i32* %b, align 4
81 %ap2 = bitcast i8** %ap to i8*
82 call void @llvm.va_end(i8* %ap2)
83 %tmp = load i32* %b, align 4
87 ; CHECK: addiu $sp, $sp, -40
88 ; CHECK: sw $6, 48($sp)
89 ; CHECK: sw $7, 52($sp)
90 ; CHECK: lw $2, 48($sp)
94 define double @va4(double %a, ...) nounwind {
96 %a.addr = alloca double, align 8
97 %ap = alloca i8*, align 4
98 %b = alloca double, align 8
99 store double %a, double* %a.addr, align 8
100 %ap1 = bitcast i8** %ap to i8*
101 call void @llvm.va_start(i8* %ap1)
102 %0 = va_arg i8** %ap, double
103 store double %0, double* %b, align 8
104 %ap2 = bitcast i8** %ap to i8*
105 call void @llvm.va_end(i8* %ap2)
106 %tmp = load double* %b, align 8
110 ; CHECK: addiu $sp, $sp, -48
111 ; CHECK: sw $6, 56($sp)
112 ; CHECK: sw $7, 60($sp)
113 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
114 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
115 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
116 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
117 ; CHECK: ldc1 $f0, 0($[[R3]])
121 define i32 @va5(i32 %a, i32 %b, i32 %c, ...) nounwind {
123 %a.addr = alloca i32, align 4
124 %b.addr = alloca i32, align 4
125 %c.addr = alloca i32, align 4
126 %ap = alloca i8*, align 4
127 %d = alloca i32, align 4
128 store i32 %a, i32* %a.addr, align 4
129 store i32 %b, i32* %b.addr, align 4
130 store i32 %c, i32* %c.addr, align 4
131 %ap1 = bitcast i8** %ap to i8*
132 call void @llvm.va_start(i8* %ap1)
133 %0 = va_arg i8** %ap, i32
134 store i32 %0, i32* %d, align 4
135 %ap2 = bitcast i8** %ap to i8*
136 call void @llvm.va_end(i8* %ap2)
137 %tmp = load i32* %d, align 4
141 ; CHECK: addiu $sp, $sp, -40
142 ; CHECK: sw $7, 52($sp)
143 ; CHECK: lw $2, 52($sp)
147 define double @va6(i32 %a, i32 %b, i32 %c, ...) nounwind {
149 %a.addr = alloca i32, align 4
150 %b.addr = alloca i32, align 4
151 %c.addr = alloca i32, align 4
152 %ap = alloca i8*, align 4
153 %d = alloca double, align 8
154 store i32 %a, i32* %a.addr, align 4
155 store i32 %b, i32* %b.addr, align 4
156 store i32 %c, i32* %c.addr, align 4
157 %ap1 = bitcast i8** %ap to i8*
158 call void @llvm.va_start(i8* %ap1)
159 %0 = va_arg i8** %ap, double
160 store double %0, double* %d, align 8
161 %ap2 = bitcast i8** %ap to i8*
162 call void @llvm.va_end(i8* %ap2)
163 %tmp = load double* %d, align 8
167 ; CHECK: addiu $sp, $sp, -48
168 ; CHECK: sw $7, 60($sp)
169 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
170 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
171 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
172 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
173 ; CHECK: ldc1 $f0, 0($[[R3]])
177 define i32 @va7(i32 %a, double %b, ...) nounwind {
179 %a.addr = alloca i32, align 4
180 %b.addr = alloca double, align 8
181 %ap = alloca i8*, align 4
182 %c = alloca i32, align 4
183 store i32 %a, i32* %a.addr, align 4
184 store double %b, double* %b.addr, align 8
185 %ap1 = bitcast i8** %ap to i8*
186 call void @llvm.va_start(i8* %ap1)
187 %0 = va_arg i8** %ap, i32
188 store i32 %0, i32* %c, align 4
189 %ap2 = bitcast i8** %ap to i8*
190 call void @llvm.va_end(i8* %ap2)
191 %tmp = load i32* %c, align 4
195 ; CHECK: addiu $sp, $sp, -40
196 ; CHECK: lw $2, 56($sp)
200 define double @va8(i32 %a, double %b, ...) nounwind {
202 %a.addr = alloca i32, align 4
203 %b.addr = alloca double, align 8
204 %ap = alloca i8*, align 4
205 %c = alloca double, align 8
206 store i32 %a, i32* %a.addr, align 4
207 store double %b, double* %b.addr, align 8
208 %ap1 = bitcast i8** %ap to i8*
209 call void @llvm.va_start(i8* %ap1)
210 %0 = va_arg i8** %ap, double
211 store double %0, double* %c, align 8
212 %ap2 = bitcast i8** %ap to i8*
213 call void @llvm.va_end(i8* %ap2)
214 %tmp = load double* %c, align 8
218 ; CHECK: addiu $sp, $sp, -48
219 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
220 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
221 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
222 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
223 ; CHECK: ldc1 $f0, 0($[[R3]])
227 define i32 @va9(double %a, double %b, i32 %c, ...) nounwind {
229 %a.addr = alloca double, align 8
230 %b.addr = alloca double, align 8
231 %c.addr = alloca i32, align 4
232 %ap = alloca i8*, align 4
233 %d = alloca i32, align 4
234 store double %a, double* %a.addr, align 8
235 store double %b, double* %b.addr, align 8
236 store i32 %c, i32* %c.addr, align 4
237 %ap1 = bitcast i8** %ap to i8*
238 call void @llvm.va_start(i8* %ap1)
239 %0 = va_arg i8** %ap, i32
240 store i32 %0, i32* %d, align 4
241 %ap2 = bitcast i8** %ap to i8*
242 call void @llvm.va_end(i8* %ap2)
243 %tmp = load i32* %d, align 4
247 ; CHECK: addiu $sp, $sp, -56
248 ; CHECK: lw $2, 76($sp)
252 define double @va10(double %a, double %b, i32 %c, ...) nounwind {
254 %a.addr = alloca double, align 8
255 %b.addr = alloca double, align 8
256 %c.addr = alloca i32, align 4
257 %ap = alloca i8*, align 4
258 %d = alloca double, align 8
259 store double %a, double* %a.addr, align 8
260 store double %b, double* %b.addr, align 8
261 store i32 %c, i32* %c.addr, align 4
262 %ap1 = bitcast i8** %ap to i8*
263 call void @llvm.va_start(i8* %ap1)
264 %0 = va_arg i8** %ap, double
265 store double %0, double* %d, align 8
266 %ap2 = bitcast i8** %ap to i8*
267 call void @llvm.va_end(i8* %ap2)
268 %tmp = load double* %d, align 8
272 ; CHECK: addiu $sp, $sp, -56
273 ; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
274 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
275 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
276 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
277 ; CHECK: ldc1 $f0, 0($[[R3]])