1 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
3 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
4 @llvm_mips_insert_b_ARG3 = global i32 27, align 16
5 @llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
7 define void @llvm_mips_insert_b_test() nounwind {
9 %0 = load <16 x i8>* @llvm_mips_insert_b_ARG1
10 %1 = load i32* @llvm_mips_insert_b_ARG3
11 %2 = tail call <16 x i8> @llvm.mips.insert.b(<16 x i8> %0, i32 1, i32 %1)
12 store <16 x i8> %2, <16 x i8>* @llvm_mips_insert_b_RES
16 declare <16 x i8> @llvm.mips.insert.b(<16 x i8>, i32, i32) nounwind
18 ; CHECK: llvm_mips_insert_b_test:
23 ; CHECK: .size llvm_mips_insert_b_test
25 @llvm_mips_insert_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
26 @llvm_mips_insert_h_ARG3 = global i32 27, align 16
27 @llvm_mips_insert_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
29 define void @llvm_mips_insert_h_test() nounwind {
31 %0 = load <8 x i16>* @llvm_mips_insert_h_ARG1
32 %1 = load i32* @llvm_mips_insert_h_ARG3
33 %2 = tail call <8 x i16> @llvm.mips.insert.h(<8 x i16> %0, i32 1, i32 %1)
34 store <8 x i16> %2, <8 x i16>* @llvm_mips_insert_h_RES
38 declare <8 x i16> @llvm.mips.insert.h(<8 x i16>, i32, i32) nounwind
40 ; CHECK: llvm_mips_insert_h_test:
45 ; CHECK: .size llvm_mips_insert_h_test
47 @llvm_mips_insert_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
48 @llvm_mips_insert_w_ARG3 = global i32 27, align 16
49 @llvm_mips_insert_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
51 define void @llvm_mips_insert_w_test() nounwind {
53 %0 = load <4 x i32>* @llvm_mips_insert_w_ARG1
54 %1 = load i32* @llvm_mips_insert_w_ARG3
55 %2 = tail call <4 x i32> @llvm.mips.insert.w(<4 x i32> %0, i32 1, i32 %1)
56 store <4 x i32> %2, <4 x i32>* @llvm_mips_insert_w_RES
60 declare <4 x i32> @llvm.mips.insert.w(<4 x i32>, i32, i32) nounwind
62 ; CHECK: llvm_mips_insert_w_test:
67 ; CHECK: .size llvm_mips_insert_w_test