1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
3 define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
6 %1 = load <4 x float>* %a
7 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <4 x float>* %b
9 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
10 %3 = fadd <4 x float> %1, %2
11 ; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
12 store <4 x float> %3, <4 x float>* %c
13 ; CHECK-DAG: st.w [[R3]], 0($4)
16 ; CHECK: .size add_v4f32
19 define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
22 %1 = load <2 x double>* %a
23 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
24 %2 = load <2 x double>* %b
25 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
26 %3 = fadd <2 x double> %1, %2
27 ; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
28 store <2 x double> %3, <2 x double>* %c
29 ; CHECK-DAG: st.d [[R3]], 0($4)
32 ; CHECK: .size add_v2f64
35 define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
38 %1 = load <4 x float>* %a
39 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
40 %2 = load <4 x float>* %b
41 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
42 %3 = fsub <4 x float> %1, %2
43 ; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
44 store <4 x float> %3, <4 x float>* %c
45 ; CHECK-DAG: st.w [[R3]], 0($4)
48 ; CHECK: .size sub_v4f32
51 define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
54 %1 = load <2 x double>* %a
55 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
56 %2 = load <2 x double>* %b
57 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
58 %3 = fsub <2 x double> %1, %2
59 ; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
60 store <2 x double> %3, <2 x double>* %c
61 ; CHECK-DAG: st.d [[R3]], 0($4)
64 ; CHECK: .size sub_v2f64
67 define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
70 %1 = load <4 x float>* %a
71 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
72 %2 = load <4 x float>* %b
73 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
74 %3 = fmul <4 x float> %1, %2
75 ; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
76 store <4 x float> %3, <4 x float>* %c
77 ; CHECK-DAG: st.w [[R3]], 0($4)
80 ; CHECK: .size mul_v4f32
83 define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
86 %1 = load <2 x double>* %a
87 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
88 %2 = load <2 x double>* %b
89 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
90 %3 = fmul <2 x double> %1, %2
91 ; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
92 store <2 x double> %3, <2 x double>* %c
93 ; CHECK-DAG: st.d [[R3]], 0($4)
96 ; CHECK: .size mul_v2f64
99 define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
102 %1 = load <4 x float>* %a
103 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
104 %2 = load <4 x float>* %b
105 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
106 %3 = fdiv <4 x float> %1, %2
107 ; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
108 store <4 x float> %3, <4 x float>* %c
109 ; CHECK-DAG: st.w [[R3]], 0($4)
112 ; CHECK: .size fdiv_v4f32
115 define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
118 %1 = load <2 x double>* %a
119 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
120 %2 = load <2 x double>* %b
121 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
122 %3 = fdiv <2 x double> %1, %2
123 ; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
124 store <2 x double> %3, <2 x double>* %c
125 ; CHECK-DAG: st.d [[R3]], 0($4)
128 ; CHECK: .size fdiv_v2f64
131 define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
134 %1 = load <4 x float>* %a
135 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
136 %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)
137 ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
138 store <4 x float> %2, <4 x float>* %c
139 ; CHECK-DAG: st.w [[R3]], 0($4)
142 ; CHECK: .size fabs_v4f32
145 define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
148 %1 = load <2 x double>* %a
149 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
150 %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)
151 ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]
152 store <2 x double> %2, <2 x double>* %c
153 ; CHECK-DAG: st.d [[R3]], 0($4)
156 ; CHECK: .size fabs_v2f64
159 define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
160 ; CHECK: fsqrt_v4f32:
162 %1 = load <4 x float>* %a
163 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
164 %2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)
165 ; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]
166 store <4 x float> %2, <4 x float>* %c
167 ; CHECK-DAG: st.w [[R3]], 0($4)
170 ; CHECK: .size fsqrt_v4f32
173 define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
174 ; CHECK: fsqrt_v2f64:
176 %1 = load <2 x double>* %a
177 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
178 %2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)
179 ; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]
180 store <2 x double> %2, <2 x double>* %c
181 ; CHECK-DAG: st.d [[R3]], 0($4)
184 ; CHECK: .size fsqrt_v2f64
187 define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
188 ; CHECK: ffint_u_v4f32:
190 %1 = load <4 x i32>* %a
191 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
192 %2 = uitofp <4 x i32> %1 to <4 x float>
193 ; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]]
194 store <4 x float> %2, <4 x float>* %c
195 ; CHECK-DAG: st.w [[R3]], 0($4)
198 ; CHECK: .size ffint_u_v4f32
201 define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
202 ; CHECK: ffint_u_v2f64:
204 %1 = load <2 x i64>* %a
205 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
206 %2 = uitofp <2 x i64> %1 to <2 x double>
207 ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]]
208 store <2 x double> %2, <2 x double>* %c
209 ; CHECK-DAG: st.d [[R3]], 0($4)
212 ; CHECK: .size ffint_u_v2f64
215 define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
216 ; CHECK: ffint_s_v4f32:
218 %1 = load <4 x i32>* %a
219 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
220 %2 = sitofp <4 x i32> %1 to <4 x float>
221 ; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]]
222 store <4 x float> %2, <4 x float>* %c
223 ; CHECK-DAG: st.w [[R3]], 0($4)
226 ; CHECK: .size ffint_s_v4f32
229 define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
230 ; CHECK: ffint_s_v2f64:
232 %1 = load <2 x i64>* %a
233 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
234 %2 = sitofp <2 x i64> %1 to <2 x double>
235 ; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]]
236 store <2 x double> %2, <2 x double>* %c
237 ; CHECK-DAG: st.d [[R3]], 0($4)
240 ; CHECK: .size ffint_s_v2f64
243 define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
244 ; CHECK: ftrunc_u_v4f32:
246 %1 = load <4 x float>* %a
247 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
248 %2 = fptoui <4 x float> %1 to <4 x i32>
249 ; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]]
250 store <4 x i32> %2, <4 x i32>* %c
251 ; CHECK-DAG: st.w [[R3]], 0($4)
254 ; CHECK: .size ftrunc_u_v4f32
257 define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
258 ; CHECK: ftrunc_u_v2f64:
260 %1 = load <2 x double>* %a
261 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
262 %2 = fptoui <2 x double> %1 to <2 x i64>
263 ; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]]
264 store <2 x i64> %2, <2 x i64>* %c
265 ; CHECK-DAG: st.d [[R3]], 0($4)
268 ; CHECK: .size ftrunc_u_v2f64
271 define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
272 ; CHECK: ftrunc_s_v4f32:
274 %1 = load <4 x float>* %a
275 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
276 %2 = fptosi <4 x float> %1 to <4 x i32>
277 ; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]]
278 store <4 x i32> %2, <4 x i32>* %c
279 ; CHECK-DAG: st.w [[R3]], 0($4)
282 ; CHECK: .size ftrunc_s_v4f32
285 define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
286 ; CHECK: ftrunc_s_v2f64:
288 %1 = load <2 x double>* %a
289 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
290 %2 = fptosi <2 x double> %1 to <2 x i64>
291 ; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]]
292 store <2 x i64> %2, <2 x i64>* %c
293 ; CHECK-DAG: st.d [[R3]], 0($4)
296 ; CHECK: .size ftrunc_s_v2f64
299 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val)
300 declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val)
301 declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)
302 declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)