1 ; Test the MSA intrinsics that are encoded with the 3R instruction format.
2 ; There are lots of these so this covers those beginning with 'd'
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
8 @llvm_mips_div_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_div_s_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
13 %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
14 %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1)
15 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
19 declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind
21 ; CHECK: llvm_mips_div_s_b_test:
26 ; CHECK: .size llvm_mips_div_s_b_test
28 @llvm_mips_div_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
29 @llvm_mips_div_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
30 @llvm_mips_div_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32 define void @llvm_mips_div_s_h_test() nounwind {
34 %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
35 %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
36 %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1)
37 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
41 declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind
43 ; CHECK: llvm_mips_div_s_h_test:
48 ; CHECK: .size llvm_mips_div_s_h_test
50 @llvm_mips_div_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
51 @llvm_mips_div_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
52 @llvm_mips_div_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_div_s_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
57 %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
63 declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind
65 ; CHECK: llvm_mips_div_s_w_test:
70 ; CHECK: .size llvm_mips_div_s_w_test
72 @llvm_mips_div_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_div_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
74 @llvm_mips_div_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_div_s_d_test() nounwind {
78 %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
79 %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
85 declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind
87 ; CHECK: llvm_mips_div_s_d_test:
92 ; CHECK: .size llvm_mips_div_s_d_test
95 define void @div_s_b_test() nounwind {
97 %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
98 %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
99 %2 = sdiv <16 x i8> %0, %1
100 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
104 ; CHECK: div_s_b_test:
109 ; CHECK: .size div_s_b_test
111 define void @div_s_h_test() nounwind {
113 %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
114 %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
115 %2 = sdiv <8 x i16> %0, %1
116 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
120 ; CHECK: div_s_h_test:
125 ; CHECK: .size div_s_h_test
127 define void @div_s_w_test() nounwind {
129 %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
130 %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
131 %2 = sdiv <4 x i32> %0, %1
132 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
136 ; CHECK: div_s_w_test:
141 ; CHECK: .size div_s_w_test
143 define void @div_s_d_test() nounwind {
145 %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
146 %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
147 %2 = sdiv <2 x i64> %0, %1
148 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
152 ; CHECK: div_s_d_test:
157 ; CHECK: .size div_s_d_test
159 @llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
160 @llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
161 @llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
163 define void @llvm_mips_div_u_b_test() nounwind {
165 %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
166 %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
167 %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1)
168 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
172 declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind
174 ; CHECK: llvm_mips_div_u_b_test:
179 ; CHECK: .size llvm_mips_div_u_b_test
181 @llvm_mips_div_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
182 @llvm_mips_div_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
183 @llvm_mips_div_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
185 define void @llvm_mips_div_u_h_test() nounwind {
187 %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
188 %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
189 %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1)
190 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
194 declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind
196 ; CHECK: llvm_mips_div_u_h_test:
201 ; CHECK: .size llvm_mips_div_u_h_test
203 @llvm_mips_div_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
204 @llvm_mips_div_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
205 @llvm_mips_div_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
207 define void @llvm_mips_div_u_w_test() nounwind {
209 %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
210 %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
211 %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1)
212 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
216 declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind
218 ; CHECK: llvm_mips_div_u_w_test:
223 ; CHECK: .size llvm_mips_div_u_w_test
225 @llvm_mips_div_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
226 @llvm_mips_div_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
227 @llvm_mips_div_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
229 define void @llvm_mips_div_u_d_test() nounwind {
231 %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
232 %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
233 %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1)
234 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
238 declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind
240 ; CHECK: llvm_mips_div_u_d_test:
245 ; CHECK: .size llvm_mips_div_u_d_test
248 define void @div_u_b_test() nounwind {
250 %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
251 %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
252 %2 = udiv <16 x i8> %0, %1
253 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
257 ; CHECK: div_u_b_test:
262 ; CHECK: .size div_u_b_test
264 define void @div_u_h_test() nounwind {
266 %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
267 %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
268 %2 = udiv <8 x i16> %0, %1
269 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
273 ; CHECK: div_u_h_test:
278 ; CHECK: .size div_u_h_test
280 define void @div_u_w_test() nounwind {
282 %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
283 %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
284 %2 = udiv <4 x i32> %0, %1
285 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
289 ; CHECK: div_u_w_test:
294 ; CHECK: .size div_u_w_test
296 define void @div_u_d_test() nounwind {
298 %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
299 %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
300 %2 = udiv <2 x i64> %0, %1
301 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
305 ; CHECK: div_u_d_test:
310 ; CHECK: .size div_u_d_test
312 @llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
313 i8 4, i8 5, i8 6, i8 7,
314 i8 8, i8 9, i8 10, i8 11,
315 i8 12, i8 13, i8 14, i8 15>,
317 @llvm_mips_dotp_s_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
318 i8 20, i8 21, i8 22, i8 23,
319 i8 24, i8 25, i8 26, i8 27,
320 i8 28, i8 29, i8 30, i8 31>,
322 @llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
323 i16 0, i16 0, i16 0, i16 0>,
326 define void @llvm_mips_dotp_s_h_test() nounwind {
328 %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1
329 %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2
330 %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1)
331 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES
335 declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind
337 ; CHECK: llvm_mips_dotp_s_h_test:
342 ; CHECK: .size llvm_mips_dotp_s_h_test
344 @llvm_mips_dotp_s_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
345 i16 4, i16 5, i16 6, i16 7>,
347 @llvm_mips_dotp_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
348 i16 8, i16 9, i16 10, i16 11>,
350 @llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
353 define void @llvm_mips_dotp_s_w_test() nounwind {
355 %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1
356 %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2
357 %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1)
358 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES
362 declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind
364 ; CHECK: llvm_mips_dotp_s_w_test:
369 ; CHECK: .size llvm_mips_dotp_s_w_test
371 @llvm_mips_dotp_s_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
373 @llvm_mips_dotp_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
375 @llvm_mips_dotp_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
377 define void @llvm_mips_dotp_s_d_test() nounwind {
379 %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1
380 %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2
381 %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1)
382 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES
386 declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind
388 ; CHECK: llvm_mips_dotp_s_d_test:
393 ; CHECK: .size llvm_mips_dotp_s_d_test
395 @llvm_mips_dotp_u_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
396 i8 4, i8 5, i8 6, i8 7,
397 i8 8, i8 9, i8 10, i8 11,
398 i8 12, i8 13, i8 14, i8 15>,
400 @llvm_mips_dotp_u_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
401 i8 20, i8 21, i8 22, i8 23,
402 i8 24, i8 25, i8 26, i8 27,
403 i8 28, i8 29, i8 30, i8 31>,
405 @llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
406 i16 0, i16 0, i16 0, i16 0>,
409 define void @llvm_mips_dotp_u_h_test() nounwind {
411 %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1
412 %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2
413 %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1)
414 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES
418 declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind
420 ; CHECK: llvm_mips_dotp_u_h_test:
425 ; CHECK: .size llvm_mips_dotp_u_h_test
427 @llvm_mips_dotp_u_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
428 i16 4, i16 5, i16 6, i16 7>,
430 @llvm_mips_dotp_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
431 i16 8, i16 9, i16 10, i16 11>,
433 @llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
436 define void @llvm_mips_dotp_u_w_test() nounwind {
438 %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1
439 %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2
440 %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1)
441 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES
445 declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind
447 ; CHECK: llvm_mips_dotp_u_w_test:
452 ; CHECK: .size llvm_mips_dotp_u_w_test
454 @llvm_mips_dotp_u_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
456 @llvm_mips_dotp_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
458 @llvm_mips_dotp_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
460 define void @llvm_mips_dotp_u_d_test() nounwind {
462 %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1
463 %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2
464 %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1)
465 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES
469 declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind
471 ; CHECK: llvm_mips_dotp_u_d_test:
476 ; CHECK: .size llvm_mips_dotp_u_d_test