1 ; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
2 ; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
4 @gll0 = common global i64 0, align 8
5 @gll1 = common global i64 0, align 8
7 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
10 ; ALL: daddu $2, ${{[45]}}, ${{[45]}}
11 %add = add nsw i64 %a1, %a0
15 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
18 ; ALL: dsubu $2, $4, $5
19 %sub = sub nsw i64 %a0, %a1
23 define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
26 ; ALL: and $2, ${{[45]}}, ${{[45]}}
27 %and = and i64 %a1, %a0
31 define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
34 ; ALL: or $2, ${{[45]}}, ${{[45]}}
39 define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
42 ; ALL: xor $2, ${{[45]}}, ${{[45]}}
43 %xor = xor i64 %a1, %a0
47 define i64 @f7(i64 %a0) nounwind readnone {
50 ; ALL: daddiu $2, $4, 20
51 %add = add nsw i64 %a0, 20
55 define i64 @f8(i64 %a0) nounwind readnone {
58 ; ALL: daddiu $2, $4, -20
59 %sub = add nsw i64 %a0, -20
63 define i64 @f9(i64 %a0) nounwind readnone {
66 ; ALL: andi $2, $4, 20
67 %and = and i64 %a0, 20
71 define i64 @f10(i64 %a0) nounwind readnone {
79 define i64 @f11(i64 %a0) nounwind readnone {
82 ; ALL: xori $2, $4, 20
83 %xor = xor i64 %a0, 20
87 define i64 @f12(i64 %a, i64 %b) nounwind readnone {
90 ; ALL: mult ${{[45]}}, ${{[45]}}
91 %mul = mul nsw i64 %b, %a
95 define i64 @f13(i64 %a, i64 %b) nounwind readnone {
98 ; ALL: mult ${{[45]}}, ${{[45]}}
103 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
106 ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
107 ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
108 ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
109 ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
110 ; ALL: ddiv $zero, $[[T0]], $[[T1]]
111 ; ALL: teq $[[T1]], $zero, 7
113 %0 = load i64* @gll0, align 8
114 %1 = load i64* @gll1, align 8
115 %div = sdiv i64 %0, %1
119 define i64 @f15() nounwind readnone {
122 ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
123 ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
124 ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
125 ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
126 ; ALL: ddivu $zero, $[[T0]], $[[T1]]
127 ; ALL: teq $[[T1]], $zero, 7
129 %0 = load i64* @gll0, align 8
130 %1 = load i64* @gll1, align 8
131 %div = udiv i64 %0, %1
135 define i64 @f16(i64 %a, i64 %b) nounwind readnone {
138 ; ALL: ddiv $zero, $4, $5
139 ; ALL: teq $5, $zero, 7
141 %rem = srem i64 %a, %b
145 define i64 @f17(i64 %a, i64 %b) nounwind readnone {
148 ; ALL: ddivu $zero, $4, $5
149 ; ALL: teq $5, $zero, 7
151 %rem = urem i64 %a, %b
155 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
157 define i64 @f18(i64 %X) nounwind readnone {
161 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
164 ; MIPS64: dclz $2, $4
165 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
169 define i64 @f19(i64 %X) nounwind readnone {
173 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
176 ; MIPS64: dclo $2, $4
177 %neg = xor i64 %X, -1
178 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
182 define i64 @f20(i64 %a, i64 %b) nounwind readnone {
185 ; ALL: nor $2, ${{[45]}}, ${{[45]}}
187 %neg = xor i64 %or, -1