1 ; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
2 ; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
4 @gll0 = common global i64 0, align 8
5 @gll1 = common global i64 0, align 8
7 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
10 %add = add nsw i64 %a1, %a0
14 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
17 %sub = sub nsw i64 %a0, %a1
21 define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
24 %and = and i64 %a1, %a0
28 define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
35 define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
38 %xor = xor i64 %a1, %a0
42 define i64 @f7(i64 %a0) nounwind readnone {
44 ; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
45 %add = add nsw i64 %a0, 20
49 define i64 @f8(i64 %a0) nounwind readnone {
51 ; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
52 %sub = add nsw i64 %a0, -20
56 define i64 @f9(i64 %a0) nounwind readnone {
58 ; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
59 %and = and i64 %a0, 20
63 define i64 @f10(i64 %a0) nounwind readnone {
65 ; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
70 define i64 @f11(i64 %a0) nounwind readnone {
72 ; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
73 %xor = xor i64 %a0, 20
77 define i64 @f12(i64 %a, i64 %b) nounwind readnone {
80 %mul = mul nsw i64 %b, %a
84 define i64 @f13(i64 %a, i64 %b) nounwind readnone {
91 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
94 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
95 ; CHECK: teq $[[R0]], $zero, 7
97 %0 = load i64* @gll0, align 8
98 %1 = load i64* @gll1, align 8
99 %div = sdiv i64 %0, %1
103 define i64 @f15() nounwind readnone {
106 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
107 ; CHECK: teq $[[R0]], $zero, 7
109 %0 = load i64* @gll0, align 8
110 %1 = load i64* @gll1, align 8
111 %div = udiv i64 %0, %1
115 define i64 @f16(i64 %a, i64 %b) nounwind readnone {
118 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
119 ; CHECK: teq $[[R0]], $zero, 7
121 %rem = srem i64 %a, %b
125 define i64 @f17(i64 %a, i64 %b) nounwind readnone {
128 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
129 ; CHECK: teq $[[R0]], $zero, 7
131 %rem = urem i64 %a, %b
135 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
137 define i64 @f18(i64 %X) nounwind readnone {
141 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
144 ; MIPS64: dclz $2, $4
145 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
149 define i64 @f19(i64 %X) nounwind readnone {
153 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
156 ; MIPS64: dclo $2, $4
157 %neg = xor i64 %X, -1
158 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
162 define i64 @f20(i64 %a, i64 %b) nounwind readnone {
167 %neg = xor i64 %or, -1