1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
7 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
8 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
9 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
10 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
11 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
12 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
13 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
14 ; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
15 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
16 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
17 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
18 ; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
20 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
24 ; ALL: subu $[[T0:[0-9]+]], $4, $5
25 ; ALL: sll $[[T0]], $[[T0]], 31
26 ; ALL: sra $2, $[[T0]], 31
32 define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
36 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
37 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
38 ; NOT-R2-R6: sra $2, $[[T0]], 24
40 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
41 ; R2-R6: seb $2, $[[T0:[0-9]+]]
47 define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
51 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
52 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
53 ; NOT-R2-R6: sra $2, $[[T0]], 16
55 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
56 ; R2-R6: seh $2, $[[T0:[0-9]+]]
62 define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
66 ; ALL: subu $2, $4, $5
72 define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
76 ; GP32: subu $3, $5, $7
77 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
78 ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
79 ; GP32: subu $2, $4, $[[T1]]
81 ; GP64: dsubu $2, $4, $5