1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
4 ; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
7 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
9 define i32 @false_f32(float %a, float %b) nounwind {
10 ; ALL-LABEL: false_f32:
11 ; ALL: addiu $2, $zero, 0
13 %1 = fcmp false float %a, %b
14 %2 = zext i1 %1 to i32
18 define i32 @oeq_f32(float %a, float %b) nounwind {
21 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
22 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
23 ; 32-C-DAG: c.eq.s $f12, $f14
24 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
26 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
27 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
28 ; 64-C-DAG: c.eq.s $f12, $f13
29 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
31 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
32 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
34 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
35 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
37 %1 = fcmp oeq float %a, %b
38 %2 = zext i1 %1 to i32
42 define i32 @ogt_f32(float %a, float %b) nounwind {
45 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
46 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
47 ; 32-C-DAG: c.ule.s $f12, $f14
48 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
50 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
51 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
52 ; 64-C-DAG: c.ule.s $f12, $f13
53 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
55 ; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f14, $f12
56 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
58 ; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f13, $f12
59 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
61 %1 = fcmp ogt float %a, %b
62 %2 = zext i1 %1 to i32
66 define i32 @oge_f32(float %a, float %b) nounwind {
69 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
70 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
71 ; 32-C-DAG: c.ult.s $f12, $f14
72 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
74 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
75 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
76 ; 64-C-DAG: c.ult.s $f12, $f13
77 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
79 ; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f14, $f12
80 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
82 ; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f13, $f12
83 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
85 %1 = fcmp oge float %a, %b
86 %2 = zext i1 %1 to i32
90 define i32 @olt_f32(float %a, float %b) nounwind {
93 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
94 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
95 ; 32-C-DAG: c.olt.s $f12, $f14
96 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
98 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
99 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
100 ; 64-C-DAG: c.olt.s $f12, $f13
101 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
103 ; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f14
104 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
106 ; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f13
107 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
109 %1 = fcmp olt float %a, %b
110 %2 = zext i1 %1 to i32
114 define i32 @ole_f32(float %a, float %b) nounwind {
115 ; ALL-LABEL: ole_f32:
117 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
118 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
119 ; 32-C-DAG: c.ole.s $f12, $f14
120 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
122 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
123 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
124 ; 64-C-DAG: c.ole.s $f12, $f13
125 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
127 ; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f14
128 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
130 ; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f13
131 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
133 %1 = fcmp ole float %a, %b
134 %2 = zext i1 %1 to i32
138 define i32 @one_f32(float %a, float %b) nounwind {
139 ; ALL-LABEL: one_f32:
141 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
142 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
143 ; 32-C-DAG: c.ueq.s $f12, $f14
144 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
146 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
147 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
148 ; 64-C-DAG: c.ueq.s $f12, $f13
149 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
151 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
152 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
153 ; 32-CMP-DAG: not $2, $[[T1]]
155 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
156 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
157 ; 64-CMP-DAG: not $2, $[[T1]]
159 %1 = fcmp one float %a, %b
160 %2 = zext i1 %1 to i32
164 define i32 @ord_f32(float %a, float %b) nounwind {
165 ; ALL-LABEL: ord_f32:
167 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
168 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
169 ; 32-C-DAG: c.un.s $f12, $f14
170 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
172 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
173 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
174 ; 64-C-DAG: c.un.s $f12, $f13
175 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
177 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
178 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
179 ; 32-CMP-DAG: not $2, $[[T1]]
181 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
182 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
183 ; 64-CMP-DAG: not $2, $[[T1]]
185 %1 = fcmp ord float %a, %b
186 %2 = zext i1 %1 to i32
190 define i32 @ueq_f32(float %a, float %b) nounwind {
191 ; ALL-LABEL: ueq_f32:
193 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
194 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
195 ; 32-C-DAG: c.ueq.s $f12, $f14
196 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
198 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
199 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
200 ; 64-C-DAG: c.ueq.s $f12, $f13
201 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
203 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
204 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
206 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
207 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
209 %1 = fcmp ueq float %a, %b
210 %2 = zext i1 %1 to i32
214 define i32 @ugt_f32(float %a, float %b) nounwind {
215 ; ALL-LABEL: ugt_f32:
217 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
218 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
219 ; 32-C-DAG: c.ole.s $f12, $f14
220 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
222 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
223 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
224 ; 64-C-DAG: c.ole.s $f12, $f13
225 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
227 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
228 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
230 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
231 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
233 %1 = fcmp ugt float %a, %b
234 %2 = zext i1 %1 to i32
238 define i32 @uge_f32(float %a, float %b) nounwind {
239 ; ALL-LABEL: uge_f32:
241 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
242 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
243 ; 32-C-DAG: c.olt.s $f12, $f14
244 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
246 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
247 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
248 ; 64-C-DAG: c.olt.s $f12, $f13
249 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
251 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
252 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
254 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
255 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
257 %1 = fcmp uge float %a, %b
258 %2 = zext i1 %1 to i32
262 define i32 @ult_f32(float %a, float %b) nounwind {
263 ; ALL-LABEL: ult_f32:
265 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
266 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
267 ; 32-C-DAG: c.ult.s $f12, $f14
268 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
270 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
271 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
272 ; 64-C-DAG: c.ult.s $f12, $f13
273 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
275 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
276 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
278 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
279 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
281 %1 = fcmp ult float %a, %b
282 %2 = zext i1 %1 to i32
286 define i32 @ule_f32(float %a, float %b) nounwind {
287 ; ALL-LABEL: ule_f32:
289 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
290 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
291 ; 32-C-DAG: c.ule.s $f12, $f14
292 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
294 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
295 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
296 ; 64-C-DAG: c.ule.s $f12, $f13
297 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
299 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
300 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
302 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
303 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
305 %1 = fcmp ule float %a, %b
306 %2 = zext i1 %1 to i32
310 define i32 @une_f32(float %a, float %b) nounwind {
311 ; ALL-LABEL: une_f32:
313 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
314 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
315 ; 32-C-DAG: c.eq.s $f12, $f14
316 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
318 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
319 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
320 ; 64-C-DAG: c.eq.s $f12, $f13
321 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
323 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
324 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
325 ; 32-CMP-DAG: not $2, $[[T1]]
327 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
328 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
329 ; 64-CMP-DAG: not $2, $[[T1]]
331 %1 = fcmp une float %a, %b
332 %2 = zext i1 %1 to i32
336 define i32 @uno_f32(float %a, float %b) nounwind {
337 ; ALL-LABEL: uno_f32:
339 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
340 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
341 ; 32-C-DAG: c.un.s $f12, $f14
342 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
344 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
345 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
346 ; 64-C-DAG: c.un.s $f12, $f13
347 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
349 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
350 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
352 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
353 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
355 %1 = fcmp uno float %a, %b
356 %2 = zext i1 %1 to i32
360 define i32 @true_f32(float %a, float %b) nounwind {
361 ; ALL-LABEL: true_f32:
362 ; ALL: addiu $2, $zero, 1
364 %1 = fcmp true float %a, %b
365 %2 = zext i1 %1 to i32
369 define i32 @false_f64(double %a, double %b) nounwind {
370 ; ALL-LABEL: false_f64:
371 ; ALL: addiu $2, $zero, 0
373 %1 = fcmp false double %a, %b
374 %2 = zext i1 %1 to i32
378 define i32 @oeq_f64(double %a, double %b) nounwind {
379 ; ALL-LABEL: oeq_f64:
381 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
382 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
383 ; 32-C-DAG: c.eq.d $f12, $f14
384 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
386 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
387 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
388 ; 64-C-DAG: c.eq.d $f12, $f13
389 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
391 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
392 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
394 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
395 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
397 %1 = fcmp oeq double %a, %b
398 %2 = zext i1 %1 to i32
402 define i32 @ogt_f64(double %a, double %b) nounwind {
403 ; ALL-LABEL: ogt_f64:
405 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
406 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
407 ; 32-C-DAG: c.ule.d $f12, $f14
408 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
410 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
411 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
412 ; 64-C-DAG: c.ule.d $f12, $f13
413 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
415 ; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f14, $f12
416 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
418 ; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f13, $f12
419 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
421 %1 = fcmp ogt double %a, %b
422 %2 = zext i1 %1 to i32
426 define i32 @oge_f64(double %a, double %b) nounwind {
427 ; ALL-LABEL: oge_f64:
429 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
430 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
431 ; 32-C-DAG: c.ult.d $f12, $f14
432 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
434 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
435 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
436 ; 64-C-DAG: c.ult.d $f12, $f13
437 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
439 ; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f14, $f12
440 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
442 ; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f13, $f12
443 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
445 %1 = fcmp oge double %a, %b
446 %2 = zext i1 %1 to i32
450 define i32 @olt_f64(double %a, double %b) nounwind {
451 ; ALL-LABEL: olt_f64:
453 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
454 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
455 ; 32-C-DAG: c.olt.d $f12, $f14
456 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
458 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
459 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
460 ; 64-C-DAG: c.olt.d $f12, $f13
461 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
463 ; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f14
464 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
466 ; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f13
467 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
469 %1 = fcmp olt double %a, %b
470 %2 = zext i1 %1 to i32
474 define i32 @ole_f64(double %a, double %b) nounwind {
475 ; ALL-LABEL: ole_f64:
477 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
478 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
479 ; 32-C-DAG: c.ole.d $f12, $f14
480 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
482 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
483 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
484 ; 64-C-DAG: c.ole.d $f12, $f13
485 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
487 ; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f14
488 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
490 ; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f13
491 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
493 %1 = fcmp ole double %a, %b
494 %2 = zext i1 %1 to i32
498 define i32 @one_f64(double %a, double %b) nounwind {
499 ; ALL-LABEL: one_f64:
501 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
502 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
503 ; 32-C-DAG: c.ueq.d $f12, $f14
504 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
506 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
507 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
508 ; 64-C-DAG: c.ueq.d $f12, $f13
509 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
511 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
512 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
513 ; 32-CMP-DAG: not $2, $[[T1]]
515 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
516 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
517 ; 64-CMP-DAG: not $2, $[[T1]]
519 %1 = fcmp one double %a, %b
520 %2 = zext i1 %1 to i32
524 define i32 @ord_f64(double %a, double %b) nounwind {
525 ; ALL-LABEL: ord_f64:
527 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
528 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
529 ; 32-C-DAG: c.un.d $f12, $f14
530 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
532 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
533 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
534 ; 64-C-DAG: c.un.d $f12, $f13
535 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
537 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
538 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
539 ; 32-CMP-DAG: not $2, $[[T1]]
541 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
542 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
543 ; 64-CMP-DAG: not $2, $[[T1]]
545 %1 = fcmp ord double %a, %b
546 %2 = zext i1 %1 to i32
550 define i32 @ueq_f64(double %a, double %b) nounwind {
551 ; ALL-LABEL: ueq_f64:
553 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
554 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
555 ; 32-C-DAG: c.ueq.d $f12, $f14
556 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
558 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
559 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
560 ; 64-C-DAG: c.ueq.d $f12, $f13
561 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
563 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
564 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
566 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
567 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
569 %1 = fcmp ueq double %a, %b
570 %2 = zext i1 %1 to i32
574 define i32 @ugt_f64(double %a, double %b) nounwind {
575 ; ALL-LABEL: ugt_f64:
577 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
578 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
579 ; 32-C-DAG: c.ole.d $f12, $f14
580 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
582 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
583 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
584 ; 64-C-DAG: c.ole.d $f12, $f13
585 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
587 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
588 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
590 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
591 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
593 %1 = fcmp ugt double %a, %b
594 %2 = zext i1 %1 to i32
598 define i32 @uge_f64(double %a, double %b) nounwind {
599 ; ALL-LABEL: uge_f64:
601 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
602 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
603 ; 32-C-DAG: c.olt.d $f12, $f14
604 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
606 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
607 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
608 ; 64-C-DAG: c.olt.d $f12, $f13
609 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
611 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
612 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
614 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
615 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
617 %1 = fcmp uge double %a, %b
618 %2 = zext i1 %1 to i32
622 define i32 @ult_f64(double %a, double %b) nounwind {
623 ; ALL-LABEL: ult_f64:
625 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
626 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
627 ; 32-C-DAG: c.ult.d $f12, $f14
628 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
630 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
631 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
632 ; 64-C-DAG: c.ult.d $f12, $f13
633 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
635 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
636 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
638 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
639 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
641 %1 = fcmp ult double %a, %b
642 %2 = zext i1 %1 to i32
646 define i32 @ule_f64(double %a, double %b) nounwind {
647 ; ALL-LABEL: ule_f64:
649 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
650 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
651 ; 32-C-DAG: c.ule.d $f12, $f14
652 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
654 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
655 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
656 ; 64-C-DAG: c.ule.d $f12, $f13
657 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
659 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
660 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
662 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
663 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
665 %1 = fcmp ule double %a, %b
666 %2 = zext i1 %1 to i32
670 define i32 @une_f64(double %a, double %b) nounwind {
671 ; ALL-LABEL: une_f64:
673 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
674 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
675 ; 32-C-DAG: c.eq.d $f12, $f14
676 ; 32-C-DAG: movf $[[T0]], $1, $fcc0
678 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
679 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
680 ; 64-C-DAG: c.eq.d $f12, $f13
681 ; 64-C-DAG: movf $[[T0]], $1, $fcc0
683 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
684 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
685 ; 32-CMP-DAG: not $2, $[[T1]]
687 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
688 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
689 ; 64-CMP-DAG: not $2, $[[T1]]
691 %1 = fcmp une double %a, %b
692 %2 = zext i1 %1 to i32
696 define i32 @uno_f64(double %a, double %b) nounwind {
697 ; ALL-LABEL: uno_f64:
699 ; 32-C-DAG: addiu $[[T0:2]], $zero, 0
700 ; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
701 ; 32-C-DAG: c.un.d $f12, $f14
702 ; 32-C-DAG: movt $[[T0]], $1, $fcc0
704 ; 64-C-DAG: addiu $[[T0:2]], $zero, 0
705 ; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
706 ; 64-C-DAG: c.un.d $f12, $f13
707 ; 64-C-DAG: movt $[[T0]], $1, $fcc0
709 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
710 ; 32-CMP-DAG: mfc1 $2, $[[T0]]
712 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
713 ; 64-CMP-DAG: mfc1 $2, $[[T0]]
715 %1 = fcmp uno double %a, %b
716 %2 = zext i1 %1 to i32
720 define i32 @true_f64(double %a, double %b) nounwind {
721 ; ALL-LABEL: true_f64:
722 ; ALL: addiu $2, $zero, 1
724 %1 = fcmp true double %a, %b
725 %2 = zext i1 %1 to i32