1 ; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
2 ; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
3 ; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
4 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
6 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
7 @i3 = common global i32* null, align 4
9 ; O32-DAG: lw $[[R0:[0-9]+]], %got(i3)
10 ; O32-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
11 ; O32: movn $[[R0]], $[[R1]], ${{[0-9]+}}
12 ; N64-DAG: ldr $[[R0:[0-9]+]]
13 ; N64-DAG: ld $[[R1:[0-9]+]], %got_disp(i1)
14 ; N64: movn $[[R0]], $[[R1]], ${{[0-9]+}}
15 define i32* @cmov1(i32 %s) nounwind readonly {
17 %tobool = icmp ne i32 %s, 0
18 %tmp1 = load i32** @i3, align 4
19 %cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
23 @c = global i32 1, align 4
24 @d = global i32 0, align 4
27 ; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
28 ; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
29 ; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
31 ; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
32 ; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
33 ; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
34 define i32 @cmov2(i32 %s) nounwind readonly {
36 %tobool = icmp ne i32 %s, 0
37 %tmp1 = load i32* @c, align 4
38 %tmp2 = load i32* @d, align 4
39 %cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
44 ; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
45 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
46 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
48 %cmp = icmp eq i32 %a, 234
49 %cond = select i1 %cmp, i32 %b, i32 %c
54 ; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
55 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
56 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
58 %cmp = icmp eq i32 %a, 234
59 %cond = select i1 %cmp, i64 %b, i64 %c
63 ; slti and conditional move.
66 ; (select (setgt a, N), t, f)
68 ; (movz t, (setlt a, N + 1), f)
69 ; if N + 1 fits in 16-bit.
72 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
73 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
75 define i32 @slti0(i32 %a) {
77 %cmp = icmp sgt i32 %a, 32766
78 %cond = select i1 %cmp, i32 3, i32 5
83 ; O32: slt ${{[0-9]+}}
85 define i32 @slti1(i32 %a) {
87 %cmp = icmp sgt i32 %a, 32767
88 %cond = select i1 %cmp, i32 3, i32 5
93 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
94 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
96 define i32 @slti2(i32 %a) {
98 %cmp = icmp sgt i32 %a, -32769
99 %cond = select i1 %cmp, i32 3, i32 5
104 ; O32: slt ${{[0-9]+}}
106 define i32 @slti3(i32 %a) {
108 %cmp = icmp sgt i32 %a, -32770
109 %cond = select i1 %cmp, i32 3, i32 5
115 ; N64-LABEL: slti64_0:
116 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
117 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
119 define i64 @slti64_0(i64 %a) {
121 %cmp = icmp sgt i64 %a, 32766
122 %conv = select i1 %cmp, i64 3, i64 4
126 ; N64-LABEL: slti64_1:
127 ; N64: slt ${{[0-9]+}}
129 define i64 @slti64_1(i64 %a) {
131 %cmp = icmp sgt i64 %a, 32767
132 %conv = select i1 %cmp, i64 3, i64 4
136 ; N64-LABEL: slti64_2:
137 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
138 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
140 define i64 @slti64_2(i64 %a) {
142 %cmp = icmp sgt i64 %a, -32769
143 %conv = select i1 %cmp, i64 3, i64 4
147 ; N64-LABEL: slti64_3:
148 ; N64: slt ${{[0-9]+}}
150 define i64 @slti64_3(i64 %a) {
152 %cmp = icmp sgt i64 %a, -32770
153 %conv = select i1 %cmp, i64 3, i64 4
157 ; sltiu instructions.
160 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
161 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
163 define i32 @sltiu0(i32 %a) {
165 %cmp = icmp ugt i32 %a, 32766
166 %cond = select i1 %cmp, i32 3, i32 5
171 ; O32: sltu ${{[0-9]+}}
173 define i32 @sltiu1(i32 %a) {
175 %cmp = icmp ugt i32 %a, 32767
176 %cond = select i1 %cmp, i32 3, i32 5
181 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
182 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
184 define i32 @sltiu2(i32 %a) {
186 %cmp = icmp ugt i32 %a, -32769
187 %cond = select i1 %cmp, i32 3, i32 5
192 ; O32: sltu ${{[0-9]+}}
194 define i32 @sltiu3(i32 %a) {
196 %cmp = icmp ugt i32 %a, -32770
197 %cond = select i1 %cmp, i32 3, i32 5
202 ; (select (setxx a, N), x, x-1) or
203 ; (select (setxx a, N), x-1, x)
204 ; doesn't generate conditional moves
205 ; for constant operands whose difference is |1|
207 define i32 @slti4(i32 %a) nounwind readnone {
208 %1 = icmp slt i32 %a, 7
209 %2 = select i1 %1, i32 4, i32 3
214 ; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
215 ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3
219 define i32 @slti5(i32 %a) nounwind readnone {
220 %1 = icmp slt i32 %a, 7
221 %2 = select i1 %1, i32 -3, i32 -4
226 ; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
227 ; O32-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4
231 define i32 @slti6(i32 %a) nounwind readnone {
232 %1 = icmp slt i32 %a, 7
233 %2 = select i1 %1, i32 3, i32 4
238 ; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
239 ; O32-DAG: xori [[R1]], [[R1]], 1
240 ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3