1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \
2 ; RUN: -fast-isel -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
4 define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {
8 ; FIXME: The following instruction is redundant.
9 ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
10 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
11 ; CHECK-NEXT: movn $6, $5, $[[T1]]
13 %cond = icmp ne i1 %j, 0
14 %res = select i1 %cond, i1 %k, i1 %l
18 define i8 @sel_i8(i8 %j, i8 %k, i8 %l) {
20 ; CHECK-LABEL: sel_i8:
22 ; CHECK-DAG: seb $[[T0:[0-9]+]], $4
23 ; FIXME: The following 2 instructions are redundant.
24 ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero
25 ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
26 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
27 ; CHECK-NEXT: movn $6, $5, $[[T3]]
29 %cond = icmp ne i8 %j, 0
30 %res = select i1 %cond, i8 %k, i8 %l
34 define i16 @sel_i16(i16 %j, i16 %k, i16 %l) {
36 ; CHECK-LABEL: sel_i16:
38 ; CHECK-DAG: seh $[[T0:[0-9]+]], $4
39 ; FIXME: The following 2 instructions are redundant.
40 ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero
41 ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
42 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
43 ; CHECK-NEXT: movn $6, $5, $[[T3]]
45 %cond = icmp ne i16 %j, 0
46 %res = select i1 %cond, i16 %k, i16 %l
50 define i32 @sel_i32(i32 %j, i32 %k, i32 %l) {
52 ; CHECK-LABEL: sel_i32:
54 ; FIXME: The following instruction is redundant.
55 ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
56 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
57 ; CHECK-NEXT: movn $6, $5, $[[T1]]
59 %cond = icmp ne i32 %j, 0
60 %res = select i1 %cond, i32 %k, i32 %l
64 define float @sel_float(i32 %j, float %k, float %l) {
66 ; CHECK-LABEL: sel_float:
68 ; CHECK-DAG: mtc1 $6, $f0
69 ; CHECK-DAG: mtc1 $5, $f1
70 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
71 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
72 ; CHECK: movn.s $f0, $f1, $[[T1]]
73 %cond = icmp ne i32 %j, 0
74 %res = select i1 %cond, float %k, float %l
78 define double @sel_double(i32 %j, double %k, double %l) {
80 ; CHECK-LABEL: sel_double:
82 ; CHECK-DAG: mtc1 $6, $f2
83 ; CHECK-DAG: mthc1 $7, $f2
84 ; CHECK-DAG: ldc1 $f0, 16($sp)
85 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
86 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
87 ; CHECK: movn.d $f0, $f2, $[[T1]]
88 %cond = icmp ne i32 %j, 0
89 %res = select i1 %cond, double %k, double %l