1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 \
2 ; RUN: -fast-isel -mips-fast-isel -relocation-model=pic
3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 \
4 ; RUN: -fast-isel -mips-fast-isel -relocation-model=pic
6 ; The test is just to make sure it is able to allocate
7 ; registers for this example. There was an issue with allocating AC0
8 ; after a mul instruction.
10 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
12 define i32 @foo(i32 %a, i32 %b) {
15 %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b)
16 %2 = extractvalue { i32, i1 } %1, 0